[rtl] fix popcount & voita.

qinjun-li · qinjun-li · commit c030f8a958c3 · 2025-01-07T12:06:37.000+08:00
diff --git a/t1/src/OtherUnit.scala b/t1/src/OtherUnit.scala
@@ -133,7 +133,7 @@ class OtherUnit(val parameter: OtherUnitParam) extends VFUModule with Serializab
       selectSource2
     )
   ).asUInt
-  val popCountResult: UInt = popCount.resp + request.popInit(7, 0)
+  val popCountResult: UInt = popCount.resp + request.popInit
   val result:         UInt = Mux1H(
     resultSelect,
     Seq(ffo.resp.bits, popCountResult, indexRes, clipResult, request.src.head, request.src(1))
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -720,7 +720,7 @@ class MaskUnit(val parameter: T1Parameter)
   val readTypeRequestDeq: Bool =
     (anyReadFire && groupReadFinish) || (readIssueStageValid && readIssueStageState.needRead === 0.U)
 
-  val compressUnitResultQueue: QueueIO[CompressOutput] = Queue.io(new CompressOutput(compressParam), 2, flow = true)
+  val compressUnitResultQueue: QueueIO[CompressOutput] = Queue.io(new CompressOutput(compressParam), 4, flow = true)
 
   val noSourceValid:        Bool = noSource && counterValid &&
     (instReg.vl.orR || (mvRd && !readVS1Reg.sendToExecution))

Original file line number	Diff line number	Diff line change
`@@ -133,7 +133,7 @@ class OtherUnit(val parameter: OtherUnitParam) extends VFUModule with Serializab`
`133`	`133`	`selectSource2`
`134`	`134`	`)`
`135`	`135`	`).asUInt`
`136`		`- val popCountResult: UInt = popCount.resp + request.popInit(7, 0)`
	`136`	`+ val popCountResult: UInt = popCount.resp + request.popInit`
`137`	`137`	`val result: UInt = Mux1H(`
`138`	`138`	`resultSelect,`
`139`	`139`	`Seq(ffo.resp.bits, popCountResult, indexRes, clipResult, request.src.head, request.src(1))`