From 2d48bbc7d4d3958e42f79ad4264431331f7cf2ea Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Wed, 27 Nov 2024 05:16:50 +0800 Subject: [PATCH 01/11] [config] turn blastoise into p0rp1w --- designs/org.chipsalliance.t1.elaborator.t1.T1.toml | 2 +- designs/org.chipsalliance.t1.elaborator.t1emu.TestBench.toml | 2 +- .../org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml | 2 +- .../org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/designs/org.chipsalliance.t1.elaborator.t1.T1.toml b/designs/org.chipsalliance.t1.elaborator.t1.T1.toml index 33dfa33427..1a974bac43 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1.T1.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1.T1.toml @@ -2,7 +2,7 @@ [rookidee] cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" [blastoise] -cmdopt = "--dLen 256 --extensions zvl2048b --extensions zve32f --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +cmdopt = "--dLen 256 --extensions zvl2048b --extensions zve32f --vrfBankSize 4 --vrfRamType p0rp1w --vfuInstantiateParameter small" # Physcial Design Benchmark ## VLEN from 128 to 64K diff --git a/designs/org.chipsalliance.t1.elaborator.t1emu.TestBench.toml b/designs/org.chipsalliance.t1.elaborator.t1emu.TestBench.toml index fdebc40dcf..231e8080d2 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1emu.TestBench.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1emu.TestBench.toml @@ -1,7 +1,7 @@ [rookidee] cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" [blastoise] -cmdopt = "--dLen 256 --extensions zvl2048b --extensions zve32f --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +cmdopt = "--dLen 256 --extensions zvl2048b --extensions zve32f --vrfBankSize 4 --vrfRamType p0rp1w --vfuInstantiateParameter small" [benchmark_dlen128_vlen128] diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml index a220f52f78..47a861c30c 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml @@ -1,7 +1,7 @@ [rookidee] cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" [blastoise] -cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rp1w --vfuInstantiateParameter small" [benchmark_dlen128_vlen128] cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl128b --instructionSets zve32x --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter huge" diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml index 1ec2949c7a..2c3ec44834 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml @@ -1,7 +1,7 @@ [rookidee] cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" [blastoise] -cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rp1w --vfuInstantiateParameter small" [physical_design_case_0] cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl128b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" From e5402b0e7a4c42e489b193f1998c9f269136bae5 Mon Sep 17 00:00:00 2001 From: github-actions Date: Tue, 26 Nov 2024 21:48:25 +0000 Subject: [PATCH 02/11] [ci] update t1 test case cycle data --- .github/designs/blastoise/t1emu.json | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.github/designs/blastoise/t1emu.json b/.github/designs/blastoise/t1emu.json index c970c3f937..6070f93caf 100644 --- a/.github/designs/blastoise/t1emu.json +++ b/.github/designs/blastoise/t1emu.json @@ -1,23 +1,23 @@ { "pytorch.demo": 77, - "pytorch.lenet": 1117417, + "pytorch.lenet": 1118850, "pytorch.matmul": 14556, - "mlir.rvv_vp_intrinsic_add": 445, - "mlir.rvv_vp_intrinsic_add_scalable": 729, + "mlir.rvv_vp_intrinsic_add": 450, + "mlir.rvv_vp_intrinsic_add_scalable": 735, "mlir.hello": 137, - "mlir.stripmining": 8871, - "asm.mmm": 50444, - "asm.smoke": 7991, + "mlir.stripmining": 8872, + "asm.mmm": 50461, + "asm.smoke": 7514, "intrinsic.conv2d_less_m2": 2647, "intrinsic.linear_normalization": 3416, - "intrinsic.softmax": 7032, - "rvv_bench.ascii_to_utf16": 11282, - "rvv_bench.ascii_to_utf32": 4694, - "rvv_bench.byteswap": 19954, - "rvv_bench.mandelbrot": 230851, + "intrinsic.softmax": 7014, + "rvv_bench.ascii_to_utf16": 11286, + "rvv_bench.ascii_to_utf32": 4714, + "rvv_bench.byteswap": 20604, + "rvv_bench.mandelbrot": 236313, "rvv_bench.memcpy": 34534, "rvv_bench.memset": 11501, - "rvv_bench.mergelines": 24842, - "rvv_bench.strlen": 22697, - "rvv_bench.utf8_count": 151155 + "rvv_bench.mergelines": 24973, + "rvv_bench.strlen": 22724, + "rvv_bench.utf8_count": 153226 } \ No newline at end of file From a7c1f9160295586edbfdb1e6caa2bfb9c772a23a Mon Sep 17 00:00:00 2001 From: github-actions Date: Tue, 26 Nov 2024 22:06:50 +0000 Subject: [PATCH 03/11] [ci] update t1 test case cycle data --- .github/designs/blastoise/t1rocketemu.json | 708 ++++++++++----------- 1 file changed, 354 insertions(+), 354 deletions(-) diff --git a/.github/designs/blastoise/t1rocketemu.json b/.github/designs/blastoise/t1rocketemu.json index 4941279e39..642fe75887 100644 --- a/.github/designs/blastoise/t1rocketemu.json +++ b/.github/designs/blastoise/t1rocketemu.json @@ -1,91 +1,91 @@ { "asm.memcpy": 751, - "asm.mmm": 51749, - "asm.smoke": 8001, - "asm.strlen": 7986, - "asm.utf8_count": 205, - "codegen.vaadd_vv": 170452, - "codegen.vaadd_vx": 539363, - "codegen.vaaddu_vv": 170452, - "codegen.vaaddu_vx": 539363, - "codegen.vadc_vim": 45919, - "codegen.vadc_vvm": 21491, - "codegen.vadc_vxm": 65655, - "codegen.vadd_vi": 92286, - "codegen.vadd_vv": 43282, - "codegen.vadd_vx": 135925, - "codegen.vand_vi": 92591, - "codegen.vand_vv": 43282, - "codegen.vand_vx": 136518, - "codegen.vasub_vv": 170452, - "codegen.vasub_vx": 539363, - "codegen.vasubu_vv": 170452, - "codegen.vasubu_vx": 539363, - "codegen.vcompress_vm": 20612, - "codegen.vcpop_m": 3603, + "asm.mmm": 51782, + "asm.smoke": 7524, + "asm.strlen": 7989, + "asm.utf8_count": 206, + "codegen.vaadd_vv": 170268, + "codegen.vaadd_vx": 560487, + "codegen.vaaddu_vv": 170268, + "codegen.vaaddu_vx": 560487, + "codegen.vadc_vim": 47460, + "codegen.vadc_vvm": 21471, + "codegen.vadc_vxm": 67942, + "codegen.vadd_vi": 96427, + "codegen.vadd_vv": 43236, + "codegen.vadd_vx": 141209, + "codegen.vand_vi": 96423, + "codegen.vand_vv": 43236, + "codegen.vand_vx": 141561, + "codegen.vasub_vv": 170268, + "codegen.vasub_vx": 560487, + "codegen.vasubu_vv": 170268, + "codegen.vasubu_vx": 560487, + "codegen.vcompress_vm": 21017, + "codegen.vcpop_m": 3619, "codegen.vdiv_vv": 70806, - "codegen.vdiv_vx": 600887, + "codegen.vdiv_vx": 600832, "codegen.vdivu_vv": 71250, - "codegen.vdivu_vx": 632468, - "codegen.vfadd_vf": 739578, - "codegen.vfadd_vv": 154009, - "codegen.vfclass_v": 12627, - "codegen.vfcvt_f_x_v": 12623, - "codegen.vfcvt_f_xu_v": 12623, - "codegen.vfcvt_rtz_x_f_v": 12623, - "codegen.vfcvt_rtz_xu_f_v": 12623, - "codegen.vfcvt_x_f_v": 12623, - "codegen.vfcvt_xu_f_v": 12623, - "codegen.vfdiv_vf": 2361323, - "codegen.vfdiv_vv": 321742, - "codegen.vfirst_m": 3474, - "codegen.vfmacc_vf": 722309, - "codegen.vfmacc_vv": 162059, - "codegen.vfmadd_vf": 864949, - "codegen.vfmadd_vv": 162059, - "codegen.vfmax_vf": 678972, - "codegen.vfmax_vv": 161707, - "codegen.vfmerge_vfm": 499920, - "codegen.vfmin_vf": 739578, - "codegen.vfmin_vv": 161707, - "codegen.vfmsac_vf": 864949, - "codegen.vfmsac_vv": 162059, - "codegen.vfmsub_vf": 864949, - "codegen.vfmsub_vv": 162059, - "codegen.vfmul_vf": 739578, - "codegen.vfmul_vv": 160038, + "codegen.vdivu_vx": 632361, + "codegen.vfadd_vf": 769828, + "codegen.vfadd_vv": 153317, + "codegen.vfclass_v": 12595, + "codegen.vfcvt_f_x_v": 12585, + "codegen.vfcvt_f_xu_v": 12603, + "codegen.vfcvt_rtz_x_f_v": 12585, + "codegen.vfcvt_rtz_xu_f_v": 12585, + "codegen.vfcvt_x_f_v": 12585, + "codegen.vfcvt_xu_f_v": 12585, + "codegen.vfdiv_vf": 2364989, + "codegen.vfdiv_vv": 321746, + "codegen.vfirst_m": 3490, + "codegen.vfmacc_vf": 765707, + "codegen.vfmacc_vv": 160942, + "codegen.vfmadd_vf": 895224, + "codegen.vfmadd_vv": 160942, + "codegen.vfmax_vf": 715752, + "codegen.vfmax_vv": 161070, + "codegen.vfmerge_vfm": 524931, + "codegen.vfmin_vf": 769828, + "codegen.vfmin_vv": 161070, + "codegen.vfmsac_vf": 895224, + "codegen.vfmsac_vv": 160942, + "codegen.vfmsub_vf": 895224, + "codegen.vfmsub_vv": 160942, + "codegen.vfmul_vf": 769828, + "codegen.vfmul_vv": 159401, "codegen.vfmv_f_s": 13054, "codegen.vfmv_s_f": 1920, - "codegen.vfmv_v_f": 4269, - "codegen.vfnmacc_vf": 808049, - "codegen.vfnmacc_vv": 162059, - "codegen.vfnmadd_vf": 779209, - "codegen.vfnmadd_vv": 162059, - "codegen.vfnmsac_vf": 779209, - "codegen.vfnmsac_vv": 162059, - "codegen.vfnmsub_vf": 779209, - "codegen.vfnmsub_vv": 162059, - "codegen.vfrdiv_vf": 2361323, - "codegen.vfrec7_v": 12751, + "codegen.vfmv_v_f": 4311, + "codegen.vfnmacc_vf": 839910, + "codegen.vfnmacc_vv": 160942, + "codegen.vfnmadd_vf": 821021, + "codegen.vfnmadd_vv": 160942, + "codegen.vfnmsac_vf": 821021, + "codegen.vfnmsac_vv": 160942, + "codegen.vfnmsub_vf": 821021, + "codegen.vfnmsub_vv": 160942, + "codegen.vfrdiv_vf": 2364989, + "codegen.vfrec7_v": 12707, "codegen.vfredmax_vs": 242694, "codegen.vfredmin_vs": 237306, - "codegen.vfredosum_vs": 324079, + "codegen.vfredosum_vs": 324421, "codegen.vfredusum_vs": 242694, - "codegen.vfrsqrt7_v": 12623, - "codegen.vfrsub_vf": 678972, - "codegen.vfsgnj_vf": 626528, - "codegen.vfsgnj_vv": 161707, - "codegen.vfsgnjn_vf": 626528, - "codegen.vfsgnjn_vv": 154009, - "codegen.vfsgnjx_vf": 626528, - "codegen.vfsgnjx_vv": 154009, + "codegen.vfrsqrt7_v": 12599, + "codegen.vfrsub_vf": 715752, + "codegen.vfsgnj_vf": 650634, + "codegen.vfsgnj_vv": 161070, + "codegen.vfsgnjn_vf": 650634, + "codegen.vfsgnjn_vv": 153317, + "codegen.vfsgnjx_vf": 650634, + "codegen.vfsgnjx_vv": 153317, "codegen.vfslide1down_vf": 1046438, "codegen.vfslide1up_vf": 1087754, "codegen.vfsqrt_v": 29261, - "codegen.vfsub_vf": 739578, - "codegen.vfsub_vv": 152340, + "codegen.vfsub_vf": 769828, + "codegen.vfsub_vv": 151648, "codegen.vid_v": 27213, - "codegen.viota_m": 39261, + "codegen.viota_m": 39391, "codegen.vl1re16_v": 1908, "codegen.vl1re32_v": 1908, "codegen.vl1re8_v": 1908, @@ -105,30 +105,30 @@ "codegen.vle8_v": 10366, "codegen.vle8ff_v": 47441, "codegen.vlm_v": 2029, - "codegen.vloxei16_v": 70296, - "codegen.vloxei32_v": 38176, - "codegen.vloxei8_v": 109790, - "codegen.vloxseg2ei16_v": 72994, - "codegen.vloxseg2ei32_v": 40030, - "codegen.vloxseg2ei8_v": 92582, - "codegen.vloxseg3ei16_v": 50214, - "codegen.vloxseg3ei32_v": 31833, - "codegen.vloxseg3ei8_v": 69174, - "codegen.vloxseg4ei16_v": 60893, - "codegen.vloxseg4ei32_v": 36985, - "codegen.vloxseg4ei8_v": 85794, - "codegen.vloxseg5ei16_v": 36930, - "codegen.vloxseg5ei32_v": 17456, - "codegen.vloxseg5ei8_v": 49965, - "codegen.vloxseg6ei16_v": 41905, - "codegen.vloxseg6ei32_v": 19168, - "codegen.vloxseg6ei8_v": 57313, - "codegen.vloxseg7ei16_v": 46880, - "codegen.vloxseg7ei32_v": 20880, - "codegen.vloxseg7ei8_v": 64661, - "codegen.vloxseg8ei16_v": 51855, - "codegen.vloxseg8ei32_v": 22592, - "codegen.vloxseg8ei8_v": 72009, + "codegen.vloxei16_v": 70479, + "codegen.vloxei32_v": 38287, + "codegen.vloxei8_v": 110012, + "codegen.vloxseg2ei16_v": 73156, + "codegen.vloxseg2ei32_v": 40138, + "codegen.vloxseg2ei8_v": 92767, + "codegen.vloxseg3ei16_v": 50336, + "codegen.vloxseg3ei32_v": 31918, + "codegen.vloxseg3ei8_v": 69318, + "codegen.vloxseg4ei16_v": 61015, + "codegen.vloxseg4ei32_v": 37070, + "codegen.vloxseg4ei8_v": 85938, + "codegen.vloxseg5ei16_v": 37010, + "codegen.vloxseg5ei32_v": 17504, + "codegen.vloxseg5ei8_v": 50061, + "codegen.vloxseg6ei16_v": 41985, + "codegen.vloxseg6ei32_v": 19216, + "codegen.vloxseg6ei8_v": 57409, + "codegen.vloxseg7ei16_v": 46960, + "codegen.vloxseg7ei32_v": 20928, + "codegen.vloxseg7ei8_v": 64757, + "codegen.vloxseg8ei16_v": 51935, + "codegen.vloxseg8ei32_v": 22640, + "codegen.vloxseg8ei8_v": 72105, "codegen.vlse16_v": 117195, "codegen.vlse32_v": 67665, "codegen.vlse8_v": 225387, @@ -174,134 +174,134 @@ "codegen.vlsseg8e16_v": 93473, "codegen.vlsseg8e32_v": 31739, "codegen.vlsseg8e8_v": 200085, - "codegen.vluxei16_v": 70296, - "codegen.vluxei32_v": 38176, - "codegen.vluxei8_v": 109790, - "codegen.vluxseg2ei16_v": 72994, - "codegen.vluxseg2ei32_v": 40030, - "codegen.vluxseg2ei8_v": 92582, - "codegen.vluxseg3ei16_v": 50214, - "codegen.vluxseg3ei32_v": 31833, - "codegen.vluxseg3ei8_v": 69174, - "codegen.vluxseg4ei16_v": 60893, - "codegen.vluxseg4ei32_v": 36985, - "codegen.vluxseg4ei8_v": 85794, - "codegen.vluxseg5ei16_v": 36930, - "codegen.vluxseg5ei32_v": 17456, - "codegen.vluxseg5ei8_v": 49965, - "codegen.vluxseg6ei16_v": 41905, - "codegen.vluxseg6ei32_v": 19168, - "codegen.vluxseg6ei8_v": 57313, - "codegen.vluxseg7ei16_v": 46880, - "codegen.vluxseg7ei32_v": 20880, - "codegen.vluxseg7ei8_v": 64661, - "codegen.vluxseg8ei16_v": 51855, - "codegen.vluxseg8ei32_v": 22592, - "codegen.vluxseg8ei8_v": 72009, - "codegen.vmacc_vv": 43698, - "codegen.vmacc_vx": 160470, - "codegen.vmadc_vi": 55485, - "codegen.vmadc_vim": 56097, - "codegen.vmadc_vv": 18266, - "codegen.vmadc_vvm": 20641, - "codegen.vmadc_vx": 76456, - "codegen.vmadc_vxm": 76845, - "codegen.vmadd_vv": 43698, - "codegen.vmadd_vx": 147017, - "codegen.vmand_mm": 17003, - "codegen.vmandn_mm": 17003, - "codegen.vmax_vv": 43282, - "codegen.vmax_vx": 135925, - "codegen.vmaxu_vv": 43282, - "codegen.vmaxu_vx": 135925, - "codegen.vmerge_vim": 82193, - "codegen.vmerge_vvm": 26341, - "codegen.vmerge_vxm": 115847, - "codegen.vmfeq_vf": 955379, - "codegen.vmfeq_vv": 169709, - "codegen.vmfge_vf": 964197, - "codegen.vmfgt_vf": 960809, - "codegen.vmfle_vf": 950549, - "codegen.vmfle_vv": 169709, - "codegen.vmflt_vf": 958767, - "codegen.vmflt_vv": 160277, - "codegen.vmfne_vf": 960809, - "codegen.vmfne_vv": 155775, - "codegen.vmin_vv": 43282, - "codegen.vmin_vx": 135925, - "codegen.vminu_vv": 43282, - "codegen.vminu_vx": 135925, - "codegen.vmnand_mm": 17003, - "codegen.vmnor_mm": 17003, - "codegen.vmor_mm": 17003, - "codegen.vmorn_mm": 17003, - "codegen.vmsbc_vv": 18266, - "codegen.vmsbc_vvm": 20641, - "codegen.vmsbc_vx": 76696, - "codegen.vmsbc_vxm": 77484, + "codegen.vluxei16_v": 70479, + "codegen.vluxei32_v": 38287, + "codegen.vluxei8_v": 110012, + "codegen.vluxseg2ei16_v": 73156, + "codegen.vluxseg2ei32_v": 40138, + "codegen.vluxseg2ei8_v": 92767, + "codegen.vluxseg3ei16_v": 50336, + "codegen.vluxseg3ei32_v": 31918, + "codegen.vluxseg3ei8_v": 69318, + "codegen.vluxseg4ei16_v": 61015, + "codegen.vluxseg4ei32_v": 37070, + "codegen.vluxseg4ei8_v": 85938, + "codegen.vluxseg5ei16_v": 37010, + "codegen.vluxseg5ei32_v": 17504, + "codegen.vluxseg5ei8_v": 50061, + "codegen.vluxseg6ei16_v": 41985, + "codegen.vluxseg6ei32_v": 19216, + "codegen.vluxseg6ei8_v": 57409, + "codegen.vluxseg7ei16_v": 46960, + "codegen.vluxseg7ei32_v": 20928, + "codegen.vluxseg7ei8_v": 64757, + "codegen.vluxseg8ei16_v": 51935, + "codegen.vluxseg8ei32_v": 22640, + "codegen.vluxseg8ei8_v": 72105, + "codegen.vmacc_vv": 43370, + "codegen.vmacc_vx": 164852, + "codegen.vmadc_vi": 56083, + "codegen.vmadc_vim": 56603, + "codegen.vmadc_vv": 18315, + "codegen.vmadc_vvm": 20666, + "codegen.vmadc_vx": 77370, + "codegen.vmadc_vxm": 77615, + "codegen.vmadd_vv": 43370, + "codegen.vmadd_vx": 153485, + "codegen.vmand_mm": 16999, + "codegen.vmandn_mm": 16999, + "codegen.vmax_vv": 43236, + "codegen.vmax_vx": 141209, + "codegen.vmaxu_vv": 43236, + "codegen.vmaxu_vx": 141209, + "codegen.vmerge_vim": 82632, + "codegen.vmerge_vvm": 26343, + "codegen.vmerge_vxm": 116872, + "codegen.vmfeq_vf": 956759, + "codegen.vmfeq_vv": 169721, + "codegen.vmfge_vf": 965577, + "codegen.vmfgt_vf": 962189, + "codegen.vmfle_vf": 952569, + "codegen.vmfle_vv": 169721, + "codegen.vmflt_vf": 960147, + "codegen.vmflt_vv": 160299, + "codegen.vmfne_vf": 962189, + "codegen.vmfne_vv": 155795, + "codegen.vmin_vv": 43236, + "codegen.vmin_vx": 141209, + "codegen.vminu_vv": 43236, + "codegen.vminu_vx": 141209, + "codegen.vmnand_mm": 16999, + "codegen.vmnor_mm": 16999, + "codegen.vmor_mm": 16999, + "codegen.vmorn_mm": 16999, + "codegen.vmsbc_vv": 18315, + "codegen.vmsbc_vvm": 20666, + "codegen.vmsbc_vx": 77618, + "codegen.vmsbc_vxm": 78387, "codegen.vmsbf_m": 2675, - "codegen.vmseq_vi": 112226, - "codegen.vmseq_vv": 40186, - "codegen.vmseq_vx": 153920, - "codegen.vmsgt_vi": 109902, + "codegen.vmseq_vi": 113418, + "codegen.vmseq_vv": 40220, + "codegen.vmseq_vx": 155726, + "codegen.vmsgt_vi": 110914, "codegen.vmsgt_vv": 40184, - "codegen.vmsgt_vx": 153920, - "codegen.vmsgtu_vi": 109902, + "codegen.vmsgt_vx": 155726, + "codegen.vmsgtu_vi": 110914, "codegen.vmsgtu_vv": 40184, - "codegen.vmsgtu_vx": 153920, + "codegen.vmsgtu_vx": 155726, "codegen.vmsif_m": 2736, - "codegen.vmsle_vi": 111628, - "codegen.vmsle_vv": 40186, - "codegen.vmsle_vx": 153920, - "codegen.vmsleu_vi": 110500, + "codegen.vmsle_vi": 112820, + "codegen.vmsle_vv": 40220, + "codegen.vmsle_vx": 155726, + "codegen.vmsleu_vi": 111512, "codegen.vmsleu_vv": 39180, - "codegen.vmsleu_vx": 153920, + "codegen.vmsleu_vx": 155726, "codegen.vmslt_vv": 39180, - "codegen.vmslt_vx": 153920, - "codegen.vmsltu_vv": 40186, - "codegen.vmsltu_vx": 153920, - "codegen.vmsne_vi": 111628, + "codegen.vmslt_vx": 155726, + "codegen.vmsltu_vv": 40220, + "codegen.vmsltu_vx": 155726, + "codegen.vmsne_vi": 112820, "codegen.vmsne_vv": 39180, - "codegen.vmsne_vx": 153920, + "codegen.vmsne_vx": 155726, "codegen.vmsof_m": 2736, - "codegen.vmul_vv": 43454, - "codegen.vmul_vx": 185727, - "codegen.vmulh_vv": 43454, - "codegen.vmulh_vx": 185727, - "codegen.vmulhsu_vv": 43454, - "codegen.vmulhsu_vx": 185727, - "codegen.vmulhu_vv": 43454, - "codegen.vmulhu_vx": 185727, + "codegen.vmul_vv": 43386, + "codegen.vmul_vx": 196279, + "codegen.vmulh_vv": 43386, + "codegen.vmulh_vx": 196279, + "codegen.vmulhsu_vv": 43386, + "codegen.vmulhsu_vx": 196279, + "codegen.vmulhu_vv": 43386, + "codegen.vmulhu_vx": 196279, "codegen.vmv1r_v": 2891, "codegen.vmv2r_v": 2951, "codegen.vmv4r_v": 4678, "codegen.vmv8r_v": 6838, "codegen.vmv_s_x": 2512, - "codegen.vmv_v_i": 43019, - "codegen.vmv_v_v": 18120, - "codegen.vmv_v_x": 14633, + "codegen.vmv_v_i": 43537, + "codegen.vmv_v_v": 18144, + "codegen.vmv_v_x": 14737, "codegen.vmv_x_s": 3835, - "codegen.vmxnor_mm": 17003, - "codegen.vmxor_mm": 17003, - "codegen.vnclip_wi": 336781, - "codegen.vnclip_wv": 106276, - "codegen.vnclip_wx": 464072, - "codegen.vnclipu_wi": 336781, - "codegen.vnclipu_wv": 106276, - "codegen.vnclipu_wx": 464072, - "codegen.vnmsac_vv": 43698, - "codegen.vnmsac_vx": 147017, - "codegen.vnmsub_vv": 43698, - "codegen.vnmsub_vx": 137471, - "codegen.vnsra_wi": 85095, + "codegen.vmxnor_mm": 16999, + "codegen.vmxor_mm": 16999, + "codegen.vnclip_wi": 339466, + "codegen.vnclip_wv": 106278, + "codegen.vnclip_wx": 468010, + "codegen.vnclipu_wi": 339466, + "codegen.vnclipu_wv": 106278, + "codegen.vnclipu_wx": 468010, + "codegen.vnmsac_vv": 43370, + "codegen.vnmsac_vx": 153485, + "codegen.vnmsub_vv": 43370, + "codegen.vnmsub_vx": 144332, + "codegen.vnsra_wi": 85771, "codegen.vnsra_wv": 26982, - "codegen.vnsra_wx": 116362, - "codegen.vnsrl_wi": 85095, + "codegen.vnsra_wx": 117354, + "codegen.vnsrl_wi": 85771, "codegen.vnsrl_wv": 26982, - "codegen.vnsrl_wx": 116362, - "codegen.vor_vi": 99404, - "codegen.vor_vv": 43282, - "codegen.vor_vx": 136518, + "codegen.vnsrl_wx": 117354, + "codegen.vor_vi": 102414, + "codegen.vor_vv": 43236, + "codegen.vor_vx": 141561, "codegen.vredand_vs": 46305, "codegen.vredmax_vs": 46305, "codegen.vredmaxu_vs": 46305, @@ -311,77 +311,77 @@ "codegen.vredsum_vs": 46305, "codegen.vredxor_vs": 47056, "codegen.vrem_vv": 70806, - "codegen.vrem_vx": 600887, + "codegen.vrem_vx": 600832, "codegen.vremu_vv": 71250, - "codegen.vremu_vx": 632468, - "codegen.vrgather_vi": 155978, - "codegen.vrgather_vv": 59135, - "codegen.vrgather_vx": 212658, - "codegen.vrgatherei16_vv": 45073, - "codegen.vrsub_vi": 92286, - "codegen.vrsub_vx": 135925, + "codegen.vremu_vx": 632361, + "codegen.vrgather_vi": 158432, + "codegen.vrgather_vv": 61675, + "codegen.vrgather_vx": 216423, + "codegen.vrgatherei16_vv": 46185, + "codegen.vrsub_vi": 96427, + "codegen.vrsub_vx": 141209, "codegen.vs1r_v": 1900, "codegen.vs2r_v": 2019, "codegen.vs4r_v": 2216, "codegen.vs8r_v": 3018, - "codegen.vsadd_vi": 97115, - "codegen.vsadd_vv": 44237, - "codegen.vsadd_vx": 136290, - "codegen.vsaddu_vi": 92957, - "codegen.vsaddu_vv": 44237, - "codegen.vsaddu_vx": 136290, - "codegen.vsbc_vvm": 21491, - "codegen.vsbc_vxm": 98421, + "codegen.vsadd_vi": 100346, + "codegen.vsadd_vv": 44191, + "codegen.vsadd_vx": 141575, + "codegen.vsaddu_vi": 97096, + "codegen.vsaddu_vv": 44191, + "codegen.vsaddu_vx": 141575, + "codegen.vsbc_vvm": 21471, + "codegen.vsbc_vxm": 102580, "codegen.vse16_v": 8888, "codegen.vse32_v": 7681, "codegen.vse8_v": 10145, "codegen.vsetivli": 6005, "codegen.vsetvl": 1649, "codegen.vsetvli": 18626, - "codegen.vsext_vf2": 14020, + "codegen.vsext_vf2": 14022, "codegen.vsext_vf4": 4260, - "codegen.vslide1down_vx": 381813, - "codegen.vslide1up_vx": 381808, - "codegen.vslidedown_vi": 268775, - "codegen.vslidedown_vx": 318470, - "codegen.vslideup_vi": 271550, + "codegen.vslide1down_vx": 381823, + "codegen.vslide1up_vx": 381820, + "codegen.vslidedown_vi": 269470, + "codegen.vslidedown_vx": 318812, + "codegen.vslideup_vi": 272804, "codegen.vslideup_vx": 299359, - "codegen.vsll_vi": 149697, - "codegen.vsll_vv": 50551, - "codegen.vsll_vx": 208708, + "codegen.vsll_vi": 151769, + "codegen.vsll_vv": 50558, + "codegen.vsll_vx": 212046, "codegen.vsm_v": 2062, - "codegen.vsmul_vv": 174750, - "codegen.vsmul_vx": 552247, - "codegen.vsoxei16_v": 78491, - "codegen.vsoxei32_v": 43330, - "codegen.vsoxei8_v": 120521, - "codegen.vsoxseg2ei16_v": 80978, - "codegen.vsoxseg2ei32_v": 45428, - "codegen.vsoxseg2ei8_v": 101130, - "codegen.vsoxseg3ei16_v": 57245, - "codegen.vsoxseg3ei32_v": 37006, - "codegen.vsoxseg3ei8_v": 77378, - "codegen.vsoxseg4ei16_v": 67926, - "codegen.vsoxseg4ei32_v": 42162, - "codegen.vsoxseg4ei8_v": 93998, - "codegen.vsoxseg5ei16_v": 43764, - "codegen.vsoxseg5ei32_v": 20798, - "codegen.vsoxseg5ei8_v": 58866, - "codegen.vsoxseg6ei16_v": 48739, - "codegen.vsoxseg6ei32_v": 22510, - "codegen.vsoxseg6ei8_v": 66214, - "codegen.vsoxseg7ei16_v": 53714, - "codegen.vsoxseg7ei32_v": 24222, - "codegen.vsoxseg7ei8_v": 73562, - "codegen.vsoxseg8ei16_v": 58689, - "codegen.vsoxseg8ei32_v": 25934, - "codegen.vsoxseg8ei8_v": 80910, - "codegen.vsra_vi": 149697, - "codegen.vsra_vv": 50625, - "codegen.vsra_vx": 208708, - "codegen.vsrl_vi": 149697, - "codegen.vsrl_vv": 50625, - "codegen.vsrl_vx": 208708, + "codegen.vsmul_vv": 174478, + "codegen.vsmul_vx": 580135, + "codegen.vsoxei16_v": 78707, + "codegen.vsoxei32_v": 43542, + "codegen.vsoxei8_v": 120761, + "codegen.vsoxseg2ei16_v": 81152, + "codegen.vsoxseg2ei32_v": 45534, + "codegen.vsoxseg2ei8_v": 101322, + "codegen.vsoxseg3ei16_v": 57373, + "codegen.vsoxseg3ei32_v": 37102, + "codegen.vsoxseg3ei8_v": 77522, + "codegen.vsoxseg4ei16_v": 68052, + "codegen.vsoxseg4ei32_v": 42254, + "codegen.vsoxseg4ei8_v": 94142, + "codegen.vsoxseg5ei16_v": 43843, + "codegen.vsoxseg5ei32_v": 20846, + "codegen.vsoxseg5ei8_v": 58961, + "codegen.vsoxseg6ei16_v": 48818, + "codegen.vsoxseg6ei32_v": 22558, + "codegen.vsoxseg6ei8_v": 66309, + "codegen.vsoxseg7ei16_v": 53793, + "codegen.vsoxseg7ei32_v": 24270, + "codegen.vsoxseg7ei8_v": 73657, + "codegen.vsoxseg8ei16_v": 58768, + "codegen.vsoxseg8ei32_v": 25982, + "codegen.vsoxseg8ei8_v": 81005, + "codegen.vsra_vi": 151769, + "codegen.vsra_vv": 50631, + "codegen.vsra_vx": 212046, + "codegen.vsrl_vi": 151769, + "codegen.vsrl_vv": 50631, + "codegen.vsrl_vx": 212046, "codegen.vsse16_v": 137067, "codegen.vsse32_v": 92941, "codegen.vsse8_v": 228853, @@ -406,12 +406,12 @@ "codegen.vsseg8e16_v": 7660, "codegen.vsseg8e32_v": 4735, "codegen.vsseg8e8_v": 10420, - "codegen.vssra_vi": 597088, - "codegen.vssra_vv": 199512, - "codegen.vssra_vx": 1284209, - "codegen.vssrl_vi": 597088, - "codegen.vssrl_vv": 199756, - "codegen.vssrl_vx": 1284209, + "codegen.vssra_vi": 605370, + "codegen.vssra_vv": 199537, + "codegen.vssra_vx": 1309427, + "codegen.vssrl_vi": 605370, + "codegen.vssrl_vv": 199780, + "codegen.vssrl_vx": 1309427, "codegen.vssseg2e16_v": 130577, "codegen.vssseg2e32_v": 80467, "codegen.vssseg2e8_v": 211152, @@ -433,96 +433,96 @@ "codegen.vssseg8e16_v": 113525, "codegen.vssseg8e32_v": 44831, "codegen.vssseg8e8_v": 218268, - "codegen.vssub_vv": 43282, - "codegen.vssub_vx": 205043, - "codegen.vssubu_vv": 43282, - "codegen.vssubu_vx": 205043, - "codegen.vsub_vv": 43282, - "codegen.vsub_vx": 205043, - "codegen.vsuxei16_v": 78491, - "codegen.vsuxei32_v": 43330, - "codegen.vsuxei8_v": 120521, - "codegen.vsuxseg2ei16_v": 80978, - "codegen.vsuxseg2ei32_v": 45428, - "codegen.vsuxseg2ei8_v": 101130, - "codegen.vsuxseg3ei16_v": 57245, - "codegen.vsuxseg3ei32_v": 37006, - "codegen.vsuxseg3ei8_v": 77378, - "codegen.vsuxseg4ei16_v": 67926, - "codegen.vsuxseg4ei32_v": 42162, - "codegen.vsuxseg4ei8_v": 93998, - "codegen.vsuxseg5ei16_v": 43764, - "codegen.vsuxseg5ei32_v": 20798, - "codegen.vsuxseg5ei8_v": 58866, - "codegen.vsuxseg6ei16_v": 48739, - "codegen.vsuxseg6ei32_v": 22510, - "codegen.vsuxseg6ei8_v": 66214, - "codegen.vsuxseg7ei16_v": 53714, - "codegen.vsuxseg7ei32_v": 24222, - "codegen.vsuxseg7ei8_v": 73562, - "codegen.vsuxseg8ei16_v": 58689, - "codegen.vsuxseg8ei32_v": 25934, - "codegen.vsuxseg8ei8_v": 80910, - "codegen.vwadd_vv": 24656, - "codegen.vwadd_vx": 84125, + "codegen.vssub_vv": 43236, + "codegen.vssub_vx": 214312, + "codegen.vssubu_vv": 43236, + "codegen.vssubu_vx": 214312, + "codegen.vsub_vv": 43236, + "codegen.vsub_vx": 214312, + "codegen.vsuxei16_v": 78707, + "codegen.vsuxei32_v": 43542, + "codegen.vsuxei8_v": 120761, + "codegen.vsuxseg2ei16_v": 81152, + "codegen.vsuxseg2ei32_v": 45534, + "codegen.vsuxseg2ei8_v": 101322, + "codegen.vsuxseg3ei16_v": 57373, + "codegen.vsuxseg3ei32_v": 37102, + "codegen.vsuxseg3ei8_v": 77522, + "codegen.vsuxseg4ei16_v": 68052, + "codegen.vsuxseg4ei32_v": 42254, + "codegen.vsuxseg4ei8_v": 94142, + "codegen.vsuxseg5ei16_v": 43843, + "codegen.vsuxseg5ei32_v": 20846, + "codegen.vsuxseg5ei8_v": 58961, + "codegen.vsuxseg6ei16_v": 48818, + "codegen.vsuxseg6ei32_v": 22558, + "codegen.vsuxseg6ei8_v": 66309, + "codegen.vsuxseg7ei16_v": 53793, + "codegen.vsuxseg7ei32_v": 24270, + "codegen.vsuxseg7ei8_v": 73657, + "codegen.vsuxseg8ei16_v": 58768, + "codegen.vsuxseg8ei32_v": 25982, + "codegen.vsuxseg8ei8_v": 81005, + "codegen.vwadd_vv": 24786, + "codegen.vwadd_vx": 89711, "codegen.vwadd_wv": 27204, - "codegen.vwadd_wx": 96683, - "codegen.vwaddu_vv": 24656, - "codegen.vwaddu_vx": 84125, + "codegen.vwadd_wx": 102539, + "codegen.vwaddu_vv": 24786, + "codegen.vwaddu_vx": 89711, "codegen.vwaddu_wv": 27237, - "codegen.vwaddu_wx": 96683, - "codegen.vwmacc_vv": 26382, - "codegen.vwmacc_vx": 116645, - "codegen.vwmaccsu_vv": 26382, - "codegen.vwmaccsu_vx": 116645, - "codegen.vwmaccu_vv": 26382, - "codegen.vwmaccu_vx": 112918, - "codegen.vwmaccus_vx": 112917, - "codegen.vwmul_vv": 24703, - "codegen.vwmul_vx": 113307, - "codegen.vwmulsu_vv": 24703, - "codegen.vwmulsu_vx": 113307, - "codegen.vwmulu_vv": 24703, - "codegen.vwmulu_vx": 113307, + "codegen.vwaddu_wx": 102539, + "codegen.vwmacc_vv": 26482, + "codegen.vwmacc_vx": 118581, + "codegen.vwmaccsu_vv": 26482, + "codegen.vwmaccsu_vx": 118581, + "codegen.vwmaccu_vv": 26482, + "codegen.vwmaccu_vx": 115068, + "codegen.vwmaccus_vx": 115067, + "codegen.vwmul_vv": 24843, + "codegen.vwmul_vx": 121999, + "codegen.vwmulsu_vv": 24843, + "codegen.vwmulsu_vx": 121999, + "codegen.vwmulu_vv": 24843, + "codegen.vwmulu_vx": 121999, "codegen.vwredsum_vs": 27746, "codegen.vwredsumu_vs": 27746, - "codegen.vwsub_vv": 24656, - "codegen.vwsub_vx": 84125, + "codegen.vwsub_vv": 24786, + "codegen.vwsub_vx": 89711, "codegen.vwsub_wv": 27204, - "codegen.vwsub_wx": 96683, - "codegen.vwsubu_vv": 24656, - "codegen.vwsubu_vx": 84125, + "codegen.vwsub_wx": 102539, + "codegen.vwsubu_vv": 24786, + "codegen.vwsubu_vx": 89711, "codegen.vwsubu_wv": 27237, - "codegen.vwsubu_wx": 96683, - "codegen.vxor_vi": 96668, - "codegen.vxor_vv": 43282, - "codegen.vxor_vx": 136518, - "codegen.vzext_vf2": 14020, - "codegen.vzext_vf4": 4333, + "codegen.vwsubu_wx": 102539, + "codegen.vxor_vi": 99624, + "codegen.vxor_vv": 43236, + "codegen.vxor_vx": 141561, + "codegen.vzext_vf2": 14022, + "codegen.vzext_vf4": 4335, "intrinsic.conv2d_less_m2": 2498, - "intrinsic.linear_normalization": 3350, - "intrinsic.matmul": 65866, - "intrinsic.softmax": 6795, - "mlir.axpy_masked": 4048, - "mlir.conv": 125859, + "intrinsic.linear_normalization": 3347, + "intrinsic.matmul": 60391, + "intrinsic.softmax": 6744, + "mlir.axpy_masked": 4179, + "mlir.conv": 125860, "mlir.hello": 131, - "mlir.matmul": 56059, - "mlir.maxvl_tail_setvl_front": 700, - "mlir.rvv_vp_intrinsic_add": 466, - "mlir.rvv_vp_intrinsic_add_scalable": 807, - "mlir.stripmining": 8882, - "mlir.vectoradd": 13236, + "mlir.matmul": 56060, + "mlir.maxvl_tail_setvl_front": 694, + "mlir.rvv_vp_intrinsic_add": 471, + "mlir.rvv_vp_intrinsic_add_scalable": 813, + "mlir.stripmining": 8883, + "mlir.vectoradd": 13237, "pytorch.demo": 31521, - "pytorch.matmul": 69793, - "rvv_bench.ascii_to_utf16": 677090, - "rvv_bench.ascii_to_utf32": 226918, - "rvv_bench.byteswap": 399524, + "pytorch.matmul": 69795, + "rvv_bench.ascii_to_utf16": 677102, + "rvv_bench.ascii_to_utf32": 226944, + "rvv_bench.byteswap": 400174, "rvv_bench.chacha20": 39957, - "rvv_bench.mandelbrot": 512683, - "rvv_bench.memcpy": 671955, + "rvv_bench.mandelbrot": 519965, + "rvv_bench.memcpy": 671957, "rvv_bench.memset": 290725, - "rvv_bench.mergelines": 564159, + "rvv_bench.mergelines": 564312, "rvv_bench.poly1305": 39957, - "rvv_bench.strlen": 219139, - "rvv_bench.utf8_count": 2283382 + "rvv_bench.strlen": 219194, + "rvv_bench.utf8_count": 2285456 } \ No newline at end of file From 7e601bc47c06834e3d5ebd70d3ce5dce7b0eec27 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Tue, 26 Nov 2024 21:50:02 +0000 Subject: [PATCH 04/11] [deps] Bump T1 dependencies --- nix/t1/dependencies/_sources/generated.json | 8 ++++---- nix/t1/dependencies/_sources/generated.nix | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/nix/t1/dependencies/_sources/generated.json b/nix/t1/dependencies/_sources/generated.json index 41fc798262..cf3323d5fd 100644 --- a/nix/t1/dependencies/_sources/generated.json +++ b/nix/t1/dependencies/_sources/generated.json @@ -41,7 +41,7 @@ }, "chisel": { "cargoLocks": null, - "date": "2024-11-21", + "date": "2024-11-26", "extract": null, "name": "chisel", "passthru": null, @@ -53,11 +53,11 @@ "name": null, "owner": "chipsalliance", "repo": "chisel", - "rev": "d06d090727c859a444df23696182d17008532ae6", - "sha256": "sha256-X//BpMTi4O0cU5Qq8SohQXwXR5QEerfr0HkfytiVqtY=", + "rev": "118502e5683430610911d8ddae21363c3e06ec01", + "sha256": "sha256-XeqlDmw5ojM8EUYKAi3kTVYX37DB6ZbiHb1rb56dg3w=", "type": "github" }, - "version": "d06d090727c859a444df23696182d17008532ae6" + "version": "118502e5683430610911d8ddae21363c3e06ec01" }, "chisel-interface": { "cargoLocks": null, diff --git a/nix/t1/dependencies/_sources/generated.nix b/nix/t1/dependencies/_sources/generated.nix index 021c62fe23..bb1c3c02df 100644 --- a/nix/t1/dependencies/_sources/generated.nix +++ b/nix/t1/dependencies/_sources/generated.nix @@ -27,15 +27,15 @@ }; chisel = { pname = "chisel"; - version = "d06d090727c859a444df23696182d17008532ae6"; + version = "118502e5683430610911d8ddae21363c3e06ec01"; src = fetchFromGitHub { owner = "chipsalliance"; repo = "chisel"; - rev = "d06d090727c859a444df23696182d17008532ae6"; + rev = "118502e5683430610911d8ddae21363c3e06ec01"; fetchSubmodules = false; - sha256 = "sha256-X//BpMTi4O0cU5Qq8SohQXwXR5QEerfr0HkfytiVqtY="; + sha256 = "sha256-XeqlDmw5ojM8EUYKAi3kTVYX37DB6ZbiHb1rb56dg3w="; }; - date = "2024-11-21"; + date = "2024-11-26"; }; chisel-interface = { pname = "chisel-interface"; From 191fdc5a9883a08e4261bebc76559e54f17b2e38 Mon Sep 17 00:00:00 2001 From: Shupei Fan Date: Mon, 25 Nov 2024 18:22:41 +0000 Subject: [PATCH 05/11] [difftest] t1rocketemu: redesign mmio devices --- difftest/dpi_t1rocketemu/src/dpi.rs | 10 +- difftest/dpi_t1rocketemu/src/drive.rs | 61 +++++-- difftest/dpi_t1rocketemu/src/interconnect.rs | 168 ++++++++++++++++++ .../src/interconnect/framebuffer.rs | 142 +++++++++++++++ difftest/dpi_t1rocketemu/src/lib.rs | 1 + 5 files changed, 363 insertions(+), 19 deletions(-) create mode 100644 difftest/dpi_t1rocketemu/src/interconnect.rs create mode 100644 difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs diff --git a/difftest/dpi_t1rocketemu/src/dpi.rs b/difftest/dpi_t1rocketemu/src/dpi.rs index 0bad32f768..65964d9c27 100644 --- a/difftest/dpi_t1rocketemu/src/dpi.rs +++ b/difftest/dpi_t1rocketemu/src/dpi.rs @@ -18,18 +18,14 @@ pub type SvBitVecVal = u32; static TARGET: DpiTarget = DpiTarget::new(); -pub(crate) struct AxiReadPayload { - pub(crate) data: Vec, -} - unsafe fn write_to_pointer(dst: *mut u8, data: &[u8]) { let dst = std::slice::from_raw_parts_mut(dst, data.len()); dst.copy_from_slice(data); } -unsafe fn fill_axi_read_payload(dst: *mut SvBitVecVal, dlen: u32, payload: &AxiReadPayload) { - assert!(payload.data.len() * 8 <= dlen as usize); - write_to_pointer(dst as *mut u8, &payload.data); +unsafe fn fill_axi_read_payload(dst: *mut SvBitVecVal, dlen: u32, payload: &[u8]) { + assert!(payload.len() * 8 <= dlen as usize); + write_to_pointer(dst as *mut u8, payload); } // Return (strobe in bit, data in byte) diff --git a/difftest/dpi_t1rocketemu/src/drive.rs b/difftest/dpi_t1rocketemu/src/drive.rs index e10fef9596..8472aaad44 100644 --- a/difftest/dpi_t1rocketemu/src/drive.rs +++ b/difftest/dpi_t1rocketemu/src/drive.rs @@ -1,5 +1,6 @@ use crate::bus::ShadowBus; use crate::dpi::*; +use crate::interconnect::{create_emu_addrspace, AddressSpace}; use crate::OnlineArgs; use crate::{get_t, EXIT_CODE, EXIT_POS}; use svdpi::SvScope; @@ -11,6 +12,7 @@ use elf::{ ElfStream, }; use std::collections::HashMap; +use std::ops::Add; use std::os::unix::fs::FileExt; use std::{fs, path::Path}; use tracing::{debug, error, info, trace}; @@ -35,7 +37,7 @@ pub(crate) struct Driver { timeout: u64, last_commit_cycle: u64, - shadow_bus: ShadowBus, + addr_space: AddressSpace, pub(crate) quit: bool, pub(crate) success: bool, @@ -43,9 +45,10 @@ pub(crate) struct Driver { impl Driver { pub(crate) fn new(scope: SvScope, args: &OnlineArgs) -> Self { + let mut addr_space = create_emu_addrspace(); // pass e_entry to rocket - let (e_entry, shadow_bus, _fn_sym_tab) = - Self::load_elf(&args.elf_file).expect("fail creating simulator"); + let (e_entry, _fn_sym_tab) = + Self::load_elf(&args.elf_file, &mut addr_space).expect("fail creating simulator"); Self { scope, @@ -56,14 +59,15 @@ impl Driver { timeout: args.timeout, last_commit_cycle: 0, - shadow_bus, + addr_space, quit: false, success: false, } } - pub fn load_elf(path: &Path) -> anyhow::Result<(u64, ShadowBus, FunctionSymTab)> { + // when error happens, `mem` may be left in an unspecified intermediate state + pub fn load_elf(path: &Path, mem: &mut AddressSpace) -> anyhow::Result<(u64, FunctionSymTab)> { let file = fs::File::open(path).with_context(|| "reading ELF file")?; let mut elf: ElfStream = ElfStream::open_stream(&file).with_context(|| "parsing ELF file")?; @@ -81,7 +85,6 @@ impl Driver { } debug!("ELF entry: 0x{:x}", elf.ehdr.e_entry); - let mut mem = ShadowBus::new(); let mut load_buffer = Vec::new(); elf.segments().iter().filter(|phdr| phdr.p_type == PT_LOAD).for_each(|phdr| { let vaddr: usize = phdr.p_vaddr.try_into().expect("fail converting vaddr(u64) to usize"); @@ -102,7 +105,7 @@ impl Driver { vaddr, filesz, phdr.p_offset, err ) }); - mem.load_mem_seg(vaddr, load_buffer.as_mut_slice()); + mem.write_mem(vaddr as u32, load_buffer.len() as u32, &load_buffer); }); // FIXME: now the symbol table doesn't contain any function value @@ -127,7 +130,7 @@ impl Driver { debug!("load_elf: symtab not found"); }; - Ok((elf.ehdr.e_entry, mem, fn_sym_tab)) + Ok((elf.ehdr.e_entry, fn_sym_tab)) } pub fn update_commit_cycle(&mut self) { @@ -135,11 +138,26 @@ impl Driver { } // data_width: AXI width (count in bits) - pub(crate) fn axi_read(&mut self, addr: u32, arsize: u32, data_width: u32) -> AxiReadPayload { + // return: Vec with len=bus_size + // if size < bus_size, the result is padded due to AXI narrow transfer rules + pub(crate) fn axi_read(&mut self, addr: u32, arsize: u32, data_width: u32) -> Vec { let bus_size = data_width / 8; let size = 1 << arsize; - let data = self.shadow_bus.read_mem_axi(addr, size, bus_size); - AxiReadPayload { data } + + assert!( + addr % size == 0 && bus_size % size == 0, + "unaligned read addr={addr:#x} size={size}B dlen={bus_size}B" + ); + + let mut data = vec![0; bus_size as usize]; + if size < bus_size { + let start = (addr % bus_size) as usize; + let end = start + (size as usize); + self.addr_space.read_mem(addr, size, &mut data[start..end]); + } else { + self.addr_space.read_mem(addr, size, &mut data); + } + data } // data_width: AXI width (count in bits) @@ -153,7 +171,26 @@ impl Driver { ) { let bus_size = data_width / 8; let size = 1 << awsize; - self.shadow_bus.write_mem_axi(addr, size, bus_size, strobe, data); + + assert!( + addr % size == 0 && bus_size % size == 0, + "unaligned write addr={addr:#x} size={size}B dlen={bus_size}B" + ); + + if size < bus_size { + let start = (addr % bus_size) as usize; + let end = start + (size as usize); + + // AXI spec says strobe outsize start..end shall be inactive, check it + assert!(strobe.iter().copied().enumerate().all(|(idx, x)| !x || (start <= idx && idx < end)), + "AXI write ill-formed [T={}] data_width={data_width}, addr=0x{addr:08x}, awsize={awsize}, strobe={strobe:?}", + get_t(), + ); + + self.addr_space.write_mem_masked(addr, size, &data[start..end], &strobe[start..end]); + } else { + self.addr_space.write_mem_masked(addr, size, data, strobe); + } } pub(crate) fn watchdog(&mut self) -> u8 { diff --git a/difftest/dpi_t1rocketemu/src/interconnect.rs b/difftest/dpi_t1rocketemu/src/interconnect.rs new file mode 100644 index 0000000000..60cc24b018 --- /dev/null +++ b/difftest/dpi_t1rocketemu/src/interconnect.rs @@ -0,0 +1,168 @@ +use std::any::Any; + +use framebuffer::FrameBuffer; + +pub mod framebuffer; + +#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)] +pub struct AddrInfo { + pub offset: u32, + pub len: u32, +} + +impl AddrInfo { + pub fn as_range(self) -> std::ops::Range { + self.offset as usize..(self.offset + self.len) as usize + } +} + +// Caller is reponsible to ensure the following conditions hold: +// addr.len > 0 +// addr.len == data.len() +// addr.len == mask.len() (if mask present) +// However, since the functions are safe, +// even if contracts violate, implementions must not break memory safety, +pub trait Device: Any + Send + Sync { + // It's OK to side have effect for mmio device + // Panic for bus error + fn mem_read(&mut self, addr: AddrInfo, data: &mut [u8]); + + // Behave as if `mem_write_masked` with full mask, + // but usually have a more optimized implementation + // Panic for bus error. + fn mem_write(&mut self, addr: AddrInfo, data: &[u8]); + + // Panic for bus error + // NOTE: even if the device does not support partial write, + // it shall check mask and behave as a full write when mask is all active + fn mem_write_masked(&mut self, addr: AddrInfo, data: &[u8], mask: &[bool]); +} + +impl DeviceExt for T {} +pub trait DeviceExt: Device + Sized { + fn with_addr(self, addr: u32, size: u32) -> DeviceEntry { + DeviceEntry { + base_and_size: (addr, size), + device: Box::new(self), + } + } +} + +pub struct RegularMemory { + data: Vec, +} + +impl RegularMemory { + pub fn with_size(size: u32) -> Self { + RegularMemory { data: vec![0; size as usize] } + } +} + +impl Device for RegularMemory { + fn mem_read(&mut self, addr: AddrInfo, data: &mut [u8]) { + let mem_data = &self.data[addr.as_range()]; + data.copy_from_slice(mem_data); + } + + fn mem_write(&mut self, addr: AddrInfo, data: &[u8]) { + let mem_data = &mut self.data[addr.as_range()]; + mem_data.copy_from_slice(data); + } + + fn mem_write_masked(&mut self, addr: AddrInfo, data: &[u8], mask: &[bool]) { + let mem_data = &mut self.data[addr.as_range()]; + memcpy_mask(mem_data, data, mask); + } +} + +fn memcpy_mask(dst: &mut [u8], src: &[u8], mask: &[bool]) { + for i in 0..mask.len() { + if mask[i] { + dst[i] = src[i]; + } + } +} + +pub struct DeviceEntry { + base_and_size: (u32, u32), + device: Box, +} + +pub struct AddressSpace { + devices: Vec, +} + +impl AddressSpace { + pub fn read_mem(&mut self, addr: u32, len: u32, data: &mut [u8]) { + assert_eq!(len as usize, data.len()); + let Some(device_idx) = self.find_device_idx(addr, len) else { + panic!("read error (no device found), addr=0x{addr:08x}, len={len}B"); + }; + + let dev_entry = &mut self.devices[device_idx]; + let addr = AddrInfo { offset: addr - dev_entry.base_and_size.0, len }; + + dev_entry.device.mem_read(addr, data); + } + + pub fn write_mem(&mut self, addr: u32, len: u32, data: &[u8]) { + assert_eq!(len as usize, data.len()); + let Some(device_idx) = self.find_device_idx(addr, len) else { + panic!("write error (no device found), addr=0x{addr:08x}, len={len}B"); + }; + + let dev_entry = &mut self.devices[device_idx]; + let addr = AddrInfo { offset: addr - dev_entry.base_and_size.0, len }; + + dev_entry.device.mem_write(addr, data); + } + + pub fn write_mem_masked(&mut self, addr: u32, len: u32, data: &[u8], mask: &[bool]) { + assert_eq!(len as usize, data.len()); + assert_eq!(len as usize, mask.len()); + let Some(device_idx) = self.find_device_idx(addr, len) else { + panic!("write error (no device found), addr=0x{addr:08x}, len={len}B"); + }; + + let dev_entry = &mut self.devices[device_idx]; + let addr = AddrInfo { offset: addr - dev_entry.base_and_size.0, len }; + + dev_entry.device.mem_write_masked(addr, data, mask); + } + + fn find_device_idx(&self, addr: u32, len: u32) -> Option { + for (idx, dev) in self.devices.iter().enumerate() { + let (base, size) = dev.base_and_size; + if base <= addr && addr - base < size { + return if addr - base + len < size { + Some(idx) + } else { + None + }; + } + } + + None + } +} + +/// Memory map: +/// - 0x0400_0000 - 0x0600_0000 : framebuffer +/// - 0x2000_0000 - 0xc000_0000 : ddr +/// - 0xc000_0000 - 0xc040_0000 : sram +pub fn create_emu_addrspace() -> AddressSpace { + const DDR_BASE: u32 = 0x2000_0000; + const DDR_SIZE: u32 = 0xa000_0000; + const SRAM_BASE: u32 = 0xc000_0000; + const SRAM_SIZE: u32 = 0x0040_0000; + + const DISPLAY_BASE: u32 = 0x0400_0000; + const DISPLAY_SIZE: u32 = 0x0200_0000; + + let devices = vec![ + RegularMemory::with_size(DDR_SIZE).with_addr(DDR_BASE, DDR_SIZE), + RegularMemory::with_size(SRAM_SIZE).with_addr(SRAM_BASE, SRAM_SIZE), + FrameBuffer::new().with_addr(DISPLAY_BASE, DISPLAY_SIZE), + ]; + AddressSpace { devices } +} diff --git a/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs b/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs new file mode 100644 index 0000000000..de38850f4e --- /dev/null +++ b/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs @@ -0,0 +1,142 @@ +use std::{env, fs::File, io::BufWriter, path::PathBuf}; + +use crate::interconnect::memcpy_mask; + +use super::{AddrInfo, Device}; + +/// Device memory layout: +/// `0x000_0000 - 0x1FF_0000` addressable frame buffer memory +/// Picture is in packed RGB24 layout, row-major. See tests/disp/simple for example. +/// DISPLAY_WIDTH * DISPLAY_HEIGHT writable, out-of-range writes will be ignored +/// `0x1FF_0000 - 0x200_0000` control registers +/// `0x1FF_0000`: read as frame counter, write to flush frame buffer as png +/// `0x1FF_0004`: output dimensions +/// 0x04-06 16bits: DISPLAY_WIDTH (currently hardcoded) +/// 0x06-08 16bits: DISPLAY_HEIGHT (currently hardcoded) +/// TODO: configurable dimension and color depth support? +/// TODO: behavior emulation closer to actual LCD display? +pub struct FrameBuffer { + vram: Vec, + frame_counter: u32, +} + +const DISPLAY_WIDTH: u32 = 960; +const DISPLAY_HEIGHT: u32 = 720; + +const REG_START: u32 = 0x1FF0000; +const REG_FLUSH: usize = 0x1FF0000; +const REG_DIM: usize = 0x1FF0020; + +impl FrameBuffer { + pub fn new() -> Self { + FrameBuffer { + vram: vec![0u8; (DISPLAY_WIDTH * DISPLAY_HEIGHT * 3) as usize], + frame_counter: 0, + } + } + + // save to '{env:DISP_OUT_DIR}/frame_{frame_counter}.png' + fn save_png(&self) -> anyhow::Result<()> { + const DEFAULT_DISP_OUT_DIR: &str = "./t1-sim-result/result/pngs"; + let out_dir = + PathBuf::from(env::var("DISP_OUT_DIR").unwrap_or_else(|_| DEFAULT_DISP_OUT_DIR.into())); + + std::fs::create_dir_all(&out_dir)?; + + let path = out_dir.join(format!("frame_{}.png", self.frame_counter)); + + let file = BufWriter::new(File::create(path)?); + + let mut encoder = png::Encoder::new(file, DISPLAY_WIDTH, DISPLAY_HEIGHT); + encoder.set_color(png::ColorType::Rgb); + encoder.set_depth(png::BitDepth::Eight); + encoder.set_srgb(png::SrgbRenderingIntent::Perceptual); + + encoder.write_header()?.write_image_data(&self.vram)?; + + Ok(()) + } + + fn reg_read(&mut self, reg_offset: u32) -> u32 { + match reg_offset { + 0 => self.frame_counter, + 4 => (DISPLAY_HEIGHT << 16) + DISPLAY_WIDTH, + + _ => panic!(), + } + } + + fn reg_write(&mut self, reg_offset: u32, value: u32) { + let _ = value; + match reg_offset { + 0 => { + self.save_png().unwrap(); + self.frame_counter += 1; + } + + _ => panic!(), + } + } +} + +impl Device for FrameBuffer { + fn mem_read(&mut self, addr: AddrInfo, data: &mut [u8]) { + if addr.offset < REG_START { + // vram access + assert!(addr.offset + addr.len <= REG_START); + + data.copy_from_slice(&self.vram[addr.as_range()]); + return; + } + + // register access + + // allows only 4-byte aligned access + assert_eq!(4, addr.len); + assert!(addr.offset % 4 == 0); + + let data: &mut [u8; 4] = data.try_into().unwrap(); + let value = self.reg_read(addr.offset - REG_START); + *data = u32::to_le_bytes(value); + } + + fn mem_write(&mut self, addr: AddrInfo, data: &[u8]) { + if addr.offset < REG_START { + // vram access + assert!(addr.offset + addr.len <= REG_START); + + self.vram[addr.as_range()].copy_from_slice(data); + return; + } + + // register access + + // allows only 4-byte aligned access + assert_eq!(4, addr.len); + assert!(addr.offset % 4 == 0); + + let value = u32::from_le_bytes(data.try_into().unwrap()); + self.reg_write(addr.offset - REG_START, value); + } + + fn mem_write_masked(&mut self, addr: AddrInfo, data: &[u8], mask: &[bool]) { + if addr.offset < REG_START { + // vram access + assert!(addr.offset + addr.len <= REG_START); + + memcpy_mask(&mut self.vram[addr.as_range()], data, mask); + return; + } + + // register access + + // allows only 4-byte aligned access + assert_eq!(4, addr.len); + assert!(addr.offset % 4 == 0); + assert!(mask.iter().all(|&x| x)); + + let data: &[u8; 4] = data.try_into().unwrap(); + let value = u32::from_le_bytes(*data); + self.reg_write(addr.offset - REG_START, value); + } +} diff --git a/difftest/dpi_t1rocketemu/src/lib.rs b/difftest/dpi_t1rocketemu/src/lib.rs index 1fd775acc6..914013351d 100644 --- a/difftest/dpi_t1rocketemu/src/lib.rs +++ b/difftest/dpi_t1rocketemu/src/lib.rs @@ -5,6 +5,7 @@ use dpi_common::plusarg::PlusArgMatcher; mod bus; pub mod dpi; pub mod drive; +mod interconnect; pub(crate) struct OnlineArgs { /// Path to the ELF file From a975a7958ba772de3b82b696b5f43376eba3521e Mon Sep 17 00:00:00 2001 From: Shupei Fan Date: Tue, 26 Nov 2024 14:09:24 +0000 Subject: [PATCH 06/11] [difftest] t1rocketemu: cleanup & remove bus --- difftest/dpi_t1emu/src/dpi.rs | 4 +- difftest/dpi_t1emu/src/drive.rs | 1 + difftest/dpi_t1rocketemu/src/bus.rs | 167 ------------------ difftest/dpi_t1rocketemu/src/bus/disp.rs | 138 --------------- difftest/dpi_t1rocketemu/src/bus/mem.rs | 40 ----- difftest/dpi_t1rocketemu/src/dpi.rs | 4 +- difftest/dpi_t1rocketemu/src/drive.rs | 8 +- .../src/interconnect/framebuffer.rs | 2 - difftest/dpi_t1rocketemu/src/lib.rs | 5 +- 9 files changed, 10 insertions(+), 359 deletions(-) delete mode 100644 difftest/dpi_t1rocketemu/src/bus.rs delete mode 100644 difftest/dpi_t1rocketemu/src/bus/disp.rs delete mode 100644 difftest/dpi_t1rocketemu/src/bus/mem.rs diff --git a/difftest/dpi_t1emu/src/dpi.rs b/difftest/dpi_t1emu/src/dpi.rs index 9ee11666a8..cf89f7ba31 100644 --- a/difftest/dpi_t1emu/src/dpi.rs +++ b/difftest/dpi_t1emu/src/dpi.rs @@ -3,8 +3,8 @@ use dpi_common::plusarg::PlusArgMatcher; use dpi_common::DpiTarget; -use std::ffi::{c_char, c_longlong}; -use tracing::{debug, error}; +use std::ffi::c_longlong; +use tracing::debug; use crate::drive::Driver; use crate::OnlineArgs; diff --git a/difftest/dpi_t1emu/src/drive.rs b/difftest/dpi_t1emu/src/drive.rs index ce9b710670..45ac997943 100644 --- a/difftest/dpi_t1emu/src/drive.rs +++ b/difftest/dpi_t1emu/src/drive.rs @@ -99,6 +99,7 @@ pub(crate) struct Driver { spike_runner: SpikeRunner, // SvScope from t1_cosim_init + #[allow(unused)] scope: SvScope, pub(crate) success: bool, diff --git a/difftest/dpi_t1rocketemu/src/bus.rs b/difftest/dpi_t1rocketemu/src/bus.rs deleted file mode 100644 index 9f5a3aa59a..0000000000 --- a/difftest/dpi_t1rocketemu/src/bus.rs +++ /dev/null @@ -1,167 +0,0 @@ -mod disp; -mod mem; - -use disp::*; -use mem::*; -use tracing::{debug, error, trace}; - -trait ShadowDevice: Send + Sync { - fn new() -> Box - where - Self: Sized; - /// addr: offset respect to the base of this device - fn read_mem(&self, addr: usize, size: usize) -> Vec; - /// addr: offset respect to the base of this device - fn write_mem(&mut self, addr: usize, data: u8); - /// addr: offset respect to the base of this device - /// strobe: signals which element in data is valid, None = all valid - fn write_mem_chunk(&mut self, addr: usize, size: usize, strobe: Option<&[bool]>, data: &[u8]); -} - -struct ShadowBusDevice { - base: usize, - size: usize, - device: Box, -} - -const MAX_DEVICES: usize = 4; - -pub(crate) struct ShadowBus { - devices: [ShadowBusDevice; MAX_DEVICES], -} - -impl ShadowBus { - /// Initiate the devices on the bus as specified in `tests/t1.ld` - /// NOTE: For some reason DDR is not aligned in the address space - pub fn new() -> Self { - const DDR_SIZE: usize = 0x80000000; - const SCALAR_SIZE: usize = 0x20000000; - const SRAM_SIZE: usize = 0x00400000; - - Self { - devices: [ - ShadowBusDevice { - base: 0x04000000, - size: 0x02000000, - device: DisplayDevice::new(), - }, - ShadowBusDevice { - base: 0x20000000, - size: SCALAR_SIZE, - device: MemDevice::::new(), - }, - ShadowBusDevice { - base: 0x40000000, - size: DDR_SIZE, - device: MemDevice::::new(), - }, - ShadowBusDevice { - base: 0xc0000000, - size: SRAM_SIZE, - device: MemDevice::::new(), - }, - ], - } - } - - // size: 1 << arsize - // bus_size: AXI bus width in bytes - // return: Vec with len=bus_size - // if size < bus_size, the result is padded due to AXI narrow transfer rules - pub fn read_mem_axi(&self, addr: u32, size: u32, bus_size: u32) -> Vec { - assert!( - addr % size == 0 && bus_size % size == 0, - "unaligned access addr={addr:#x} size={size}B dlen={bus_size}B" - ); - - let start = addr as usize; - let end = (addr + size) as usize; - - let handler = self.devices.iter().find(|d| match d { - ShadowBusDevice { base, size, device: _ } => *base <= start && end <= (*base + *size), - }); - - match handler { - Some(ShadowBusDevice { base, size: _, device }) => { - let offset = start - *base; - let data = device.read_mem(offset, size as usize); - - if size < bus_size { - let mut data_padded = vec![0; bus_size as usize]; - let start = (addr % bus_size) as usize; - let end = start + data.len(); - data_padded[start..end].copy_from_slice(&data); - - data_padded - } else { - data - } - } - None => { - panic!("read addr={addr:#x} size={size}B dlen={bus_size}B leads to nowhere!"); - vec![0; bus_size as usize] - } - } - } - - // size: 1 << awsize - // bus_size: AXI bus width in bytes - // masks: write strobes, len=bus_size - // data: write data, len=bus_size - pub fn write_mem_axi( - &mut self, - addr: u32, - size: u32, - bus_size: u32, - masks: &[bool], - data: &[u8], - ) { - assert!( - addr % size == 0 && bus_size % size == 0, - "unaligned write access addr={addr:#x} size={size}B dlen={bus_size}B" - ); - - if !masks.iter().any(|x| *x) { - trace!("Mask 0 write detected"); - return; - } - - let start = (addr & ((!bus_size) + 1)) as usize; - let end = start + bus_size as usize; - - let handler = self.devices.iter_mut().find(|d| match d { - ShadowBusDevice { base, size, device: _ } => *base <= start && end <= (*base + *size), - }); - - match handler { - Some(ShadowBusDevice { base, size: _, device }) => { - let offset = start - *base; - device.write_mem_chunk(offset, bus_size as usize, Option::from(masks), data); - } - None => { - panic!("write addr={addr:#x} size={size}B dlen={bus_size}B leads to nowhere!"); - } - } - } - - pub fn load_mem_seg(&mut self, vaddr: usize, data: &[u8]) { - let handler = self - .devices - .iter_mut() - .find(|d| match d { - ShadowBusDevice { base, size, device: _ } => { - *base <= vaddr as usize && (vaddr as usize + data.len()) <= (*base + *size) - } - }) - .unwrap_or_else(|| { - panic!( - "fail reading ELF into mem with vaddr={:#x}, len={}B: load memory to nowhere", - vaddr, - data.len() - ) - }); - - let offset = vaddr - handler.base; - handler.device.write_mem_chunk(offset, data.len(), None, data) - } -} diff --git a/difftest/dpi_t1rocketemu/src/bus/disp.rs b/difftest/dpi_t1rocketemu/src/bus/disp.rs deleted file mode 100644 index 11bb8026ca..0000000000 --- a/difftest/dpi_t1rocketemu/src/bus/disp.rs +++ /dev/null @@ -1,138 +0,0 @@ -use super::ShadowDevice; -use std::fs::File; -use std::io::BufWriter; -use std::path::PathBuf; - -/// Device memory layout: -/// `0x000_0000 - 0x1FF_0000` addressable frame buffer memory -/// Picture is in packed RGB24 layout, row-major. See tests/disp/simple for example. -/// OUTPUT_WIDTH * OUTPUT_HEIGHT writable, out-of-range writes will be ignored -/// `0x1FF_0000 - 0x200_0000` control registers -/// `0x1FF_0000`: read as frame counter, write to flush frame buffer as png -/// `0x1FF_0004`: output dimensions -/// 0x04-06 16bits: OUTPUT_WIDTH (currently fixed at 960) -/// 0x06-08 16bits: OUTPUT_HEIGHT (currently fixed at 720) -/// TODO: configurable dimension and color depth support? -/// TODO: behavior emulation closer to actual LCD display? -pub(super) struct DisplayDevice { - vram: Vec, - frame_counter: i32, -} - -const DISPLAY_WIDTH: u32 = 960; -const DISPLAY_HEIGHT: u32 = 720; - -const REG_START: usize = 0x1FF0000; -const REG_FLUSH: usize = 0x1FF0000; -const REG_DIM: usize = 0x1FF0020; - -impl ShadowDevice for DisplayDevice { - fn new() -> Box - where - Self: Sized, - { - Box::new(Self { - vram: vec![0u8; (DISPLAY_WIDTH * DISPLAY_HEIGHT * 3) as usize], - frame_counter: 0, - }) - } - - fn read_mem(&self, addr: usize, size: usize) -> Vec { - let start = addr; - let end = addr + size; - - assert!( - !(start < REG_START && end > REG_START), - "Read burst should not cross register boundary" - ); - - if start < REG_START { - self.vram_read(addr, size) - } else { - self.reg_read(addr - REG_START, size) - } - } - - fn write_mem(&mut self, addr: usize, data: u8) { - if addr < self.vram.len() { - self.vram[addr] = data; - } else if addr == REG_FLUSH { - self.encode_png().unwrap(); - self.frame_counter += 1; - } - } - - fn write_mem_chunk(&mut self, addr: usize, size: usize, strobe: Option<&[bool]>, data: &[u8]) { - let start = addr; - let end = addr + size; - - if end <= self.vram.len() { - if let Some(masks) = strobe { - masks.iter().enumerate().for_each(|(i, mask)| { - if *mask { - self.vram[addr + i] = data[i]; - } - }) - } else { - let start = addr; - let end = addr + size; - self.vram[start..end].copy_from_slice(data); - } - } else { - if let Some(masks) = strobe { - masks.iter().enumerate().for_each(|(i, mask)| { - if *mask { - self.write_mem(addr + i, data[i]); - } - }) - } else { - for i in start..end { - self.write_mem(addr + i, data[i]); - } - } - } - } -} - -impl DisplayDevice { - fn vram_read(&self, offset: usize, size: usize) -> Vec { - let mut buffer = vec![0u8; size]; - let start = std::cmp::min(self.vram.len(), offset); - let end = std::cmp::min(self.vram.len(), offset + size); - (&mut buffer[0..(start - end)]).copy_from_slice(&self.vram[start..end]); - buffer - } - - fn reg_read(&self, offset: usize, size: usize) -> Vec { - let mut buffer = vec![0u8; size]; - let counter = self.frame_counter.to_le_bytes().into_iter(); - let width = (DISPLAY_WIDTH as u16).to_le_bytes().into_iter(); - let height = (DISPLAY_HEIGHT as u16).to_le_bytes().into_iter(); - let reg_space: Vec = counter.chain(width).chain(height).collect(); - - let start = std::cmp::min(reg_space.len(), offset); - let end = std::cmp::min(reg_space.len(), offset + size); - (&mut buffer[0..(end - start)]).copy_from_slice(®_space[start..end]); - buffer - } - - fn encode_png(&self) -> anyhow::Result<()> { - let out_dir = PathBuf::from( - std::env::var("DISP_OUT_DIR").unwrap_or("./t1-sim-result/result/pngs".to_string()), - ); - std::fs::create_dir_all(&out_dir)?; - - let path = out_dir.join(format!("frame_{}.png", self.frame_counter)); - let file = File::create(path)?; - let ref mut w = BufWriter::new(file); - - let mut encoder = png::Encoder::new(w, DISPLAY_WIDTH, DISPLAY_HEIGHT); - encoder.set_color(png::ColorType::Rgb); - encoder.set_depth(png::BitDepth::Eight); - encoder.set_srgb(png::SrgbRenderingIntent::Perceptual); - - let mut writer = encoder.write_header()?; - writer.write_image_data(&self.vram)?; - Ok(()) - } -} diff --git a/difftest/dpi_t1rocketemu/src/bus/mem.rs b/difftest/dpi_t1rocketemu/src/bus/mem.rs deleted file mode 100644 index 5c8eb474ac..0000000000 --- a/difftest/dpi_t1rocketemu/src/bus/mem.rs +++ /dev/null @@ -1,40 +0,0 @@ -use super::ShadowDevice; - -pub(super) struct MemDevice { - mem: Box<[u8; SIZE]>, -} - -impl ShadowDevice for MemDevice { - fn new() -> Box - where - Self: Sized, - { - Box::new(Self { mem: vec![0u8; SIZE].try_into().unwrap() }) - } - - fn read_mem(&self, addr: usize, size: usize) -> Vec { - let start = addr; - let end = addr + size; - self.mem[start..end].to_vec() - } - - fn write_mem(&mut self, addr: usize, data: u8) { - self.mem[addr] = data; - } - - fn write_mem_chunk(&mut self, addr: usize, size: usize, strobe: Option<&[bool]>, data: &[u8]) { - // NOTE: addr & size alignment check already done in ShadowBus, and ELF load can be unaligned anyway. - - if let Some(masks) = strobe { - masks.iter().enumerate().for_each(|(i, mask)| { - if *mask { - self.mem[addr + i] = data[i]; - } - }) - } else { - let start = addr; - let end = addr + size; - self.mem[start..end].copy_from_slice(data); - } - } -} diff --git a/difftest/dpi_t1rocketemu/src/dpi.rs b/difftest/dpi_t1rocketemu/src/dpi.rs index 65964d9c27..8072a9e1aa 100644 --- a/difftest/dpi_t1rocketemu/src/dpi.rs +++ b/difftest/dpi_t1rocketemu/src/dpi.rs @@ -3,9 +3,9 @@ use dpi_common::plusarg::PlusArgMatcher; use dpi_common::DpiTarget; -use std::ffi::{c_char, c_longlong}; +use std::ffi::c_longlong; use svdpi::SvScope; -use tracing::{debug, info, trace}; +use tracing::{debug, info}; use crate::drive::Driver; use crate::OnlineArgs; diff --git a/difftest/dpi_t1rocketemu/src/drive.rs b/difftest/dpi_t1rocketemu/src/drive.rs index 8472aaad44..5e2774f386 100644 --- a/difftest/dpi_t1rocketemu/src/drive.rs +++ b/difftest/dpi_t1rocketemu/src/drive.rs @@ -1,8 +1,6 @@ -use crate::bus::ShadowBus; -use crate::dpi::*; +use crate::get_t; use crate::interconnect::{create_emu_addrspace, AddressSpace}; use crate::OnlineArgs; -use crate::{get_t, EXIT_CODE, EXIT_POS}; use svdpi::SvScope; use anyhow::Context; @@ -12,10 +10,9 @@ use elf::{ ElfStream, }; use std::collections::HashMap; -use std::ops::Add; use std::os::unix::fs::FileExt; use std::{fs, path::Path}; -use tracing::{debug, error, info, trace}; +use tracing::{debug, error, trace}; #[derive(Debug)] #[allow(dead_code)] @@ -29,6 +26,7 @@ pub type FunctionSymTab = HashMap; pub(crate) struct Driver { // SvScope from t1rocket_cosim_init + #[allow(unused)] scope: SvScope, pub(crate) dlen: u32, diff --git a/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs b/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs index de38850f4e..876055314c 100644 --- a/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs +++ b/difftest/dpi_t1rocketemu/src/interconnect/framebuffer.rs @@ -24,8 +24,6 @@ const DISPLAY_WIDTH: u32 = 960; const DISPLAY_HEIGHT: u32 = 720; const REG_START: u32 = 0x1FF0000; -const REG_FLUSH: usize = 0x1FF0000; -const REG_DIM: usize = 0x1FF0020; impl FrameBuffer { pub fn new() -> Self { diff --git a/difftest/dpi_t1rocketemu/src/lib.rs b/difftest/dpi_t1rocketemu/src/lib.rs index 914013351d..447f4a03d8 100644 --- a/difftest/dpi_t1rocketemu/src/lib.rs +++ b/difftest/dpi_t1rocketemu/src/lib.rs @@ -2,9 +2,8 @@ use std::path::PathBuf; use dpi_common::plusarg::PlusArgMatcher; -mod bus; -pub mod dpi; -pub mod drive; +mod dpi; +mod drive; mod interconnect; pub(crate) struct OnlineArgs { From d978519e159c0fd11ad8c7906e801695bf25c84a Mon Sep 17 00:00:00 2001 From: Shupei Fan Date: Tue, 26 Nov 2024 15:23:33 +0000 Subject: [PATCH 07/11] [difftest] t1rocketemu: reimplement EXIT_POS by mmio device --- difftest/dpi_t1rocketemu/src/dpi.rs | 15 +---- difftest/dpi_t1rocketemu/src/drive.rs | 11 ++-- difftest/dpi_t1rocketemu/src/interconnect.rs | 61 +++++++++++++++++-- .../src/interconnect/simctrl.rs | 60 ++++++++++++++++++ difftest/dpi_t1rocketemu/src/lib.rs | 4 -- 5 files changed, 125 insertions(+), 26 deletions(-) create mode 100644 difftest/dpi_t1rocketemu/src/interconnect/simctrl.rs diff --git a/difftest/dpi_t1rocketemu/src/dpi.rs b/difftest/dpi_t1rocketemu/src/dpi.rs index 8072a9e1aa..1d8a9c7a70 100644 --- a/difftest/dpi_t1rocketemu/src/dpi.rs +++ b/difftest/dpi_t1rocketemu/src/dpi.rs @@ -5,7 +5,7 @@ use dpi_common::plusarg::PlusArgMatcher; use dpi_common::DpiTarget; use std::ffi::c_longlong; use svdpi::SvScope; -use tracing::{debug, info}; +use tracing::debug; use crate::drive::Driver; use crate::OnlineArgs; @@ -233,16 +233,6 @@ unsafe extern "C" fn axi_write_loadStoreAXI( driver.axi_write(awaddr as u32, awsize as u32, 32, strobe, data); driver.update_commit_cycle(); - - // TODO: move it to MMIO device - if awaddr as u32 == crate::EXIT_POS { - let exit_data = u32::from_le_bytes(data.try_into().expect("slice with incorrect length")); - if exit_data == crate::EXIT_CODE { - info!("driver is ready to quit"); - driver.success = true; - driver.quit = true; - } - } }); } @@ -341,7 +331,8 @@ unsafe extern "C" fn t1_cosim_init() { #[no_mangle] unsafe extern "C" fn t1_cosim_final() { TARGET.with(|driver| { - dpi_common::util::write_perf_json(crate::get_t(), driver.success); + let success = driver.exit_flag.is_finish(); + dpi_common::util::write_perf_json(crate::get_t(), success); }); } diff --git a/difftest/dpi_t1rocketemu/src/drive.rs b/difftest/dpi_t1rocketemu/src/drive.rs index 5e2774f386..2ed461b86e 100644 --- a/difftest/dpi_t1rocketemu/src/drive.rs +++ b/difftest/dpi_t1rocketemu/src/drive.rs @@ -1,4 +1,5 @@ use crate::get_t; +use crate::interconnect::simctrl::ExitFlagRef; use crate::interconnect::{create_emu_addrspace, AddressSpace}; use crate::OnlineArgs; use svdpi::SvScope; @@ -37,13 +38,12 @@ pub(crate) struct Driver { addr_space: AddressSpace, - pub(crate) quit: bool, - pub(crate) success: bool, + pub(crate) exit_flag: ExitFlagRef, } impl Driver { pub(crate) fn new(scope: SvScope, args: &OnlineArgs) -> Self { - let mut addr_space = create_emu_addrspace(); + let (mut addr_space, exit_flag) = create_emu_addrspace(); // pass e_entry to rocket let (e_entry, _fn_sym_tab) = Self::load_elf(&args.elf_file, &mut addr_space).expect("fail creating simulator"); @@ -59,8 +59,7 @@ impl Driver { addr_space, - quit: false, - success: false, + exit_flag, } } @@ -198,7 +197,7 @@ impl Driver { let tick = get_t(); - if self.quit { + if self.exit_flag.is_finish() { trace!("[{tick}] watchdog quit"); return WATCHDOG_QUIT; } diff --git a/difftest/dpi_t1rocketemu/src/interconnect.rs b/difftest/dpi_t1rocketemu/src/interconnect.rs index 60cc24b018..ee65650f27 100644 --- a/difftest/dpi_t1rocketemu/src/interconnect.rs +++ b/difftest/dpi_t1rocketemu/src/interconnect.rs @@ -1,8 +1,10 @@ use std::any::Any; use framebuffer::FrameBuffer; +use simctrl::{ExitFlagRef, SimCtrl}; pub mod framebuffer; +pub mod simctrl; #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)] pub struct AddrInfo { @@ -23,8 +25,8 @@ impl AddrInfo { // However, since the functions are safe, // even if contracts violate, implementions must not break memory safety, pub trait Device: Any + Send + Sync { - // It's OK to side have effect for mmio device - // Panic for bus error + /// It's OK to side have effect for mmio device + /// Panic for bus error fn mem_read(&mut self, addr: AddrInfo, data: &mut [u8]); // Behave as if `mem_write_masked` with full mask, @@ -48,6 +50,50 @@ pub trait DeviceExt: Device + Sized { } } +// Represents a MMIO devices consists of 4-byte 'registers'. +// Support only 4-byte aligned read/write, not support write mask +// `offset` is offset in bytes from base address, guaranteed to be multiple of 4. +// I choose offset in byte since it's usaully better aligned with document +pub trait RegDevice { + // Panic for bus error + fn reg_read(&mut self, offset: u32) -> u32; + + // Panic for bus error + fn reg_write(&mut self, offset: u32, value: u32); +} + +impl Device for T { + fn mem_read(&mut self, addr: AddrInfo, data: &mut [u8]) { + // allows only 4-byte aligned access + assert_eq!(4, addr.len); + assert!(addr.offset % 4 == 0); + + let data: &mut [u8; 4] = data.try_into().unwrap(); + let value = self.reg_read(addr.offset); + *data = u32::to_le_bytes(value); + } + + fn mem_write(&mut self, addr: AddrInfo, data: &[u8]) { + // allows only 4-byte aligned access + assert_eq!(4, addr.len); + assert!(addr.offset % 4 == 0); + + let value = u32::from_le_bytes(data.try_into().unwrap()); + self.reg_write(addr.offset, value); + } + + fn mem_write_masked(&mut self, addr: AddrInfo, data: &[u8], mask: &[bool]) { + // allows only 4-byte aligned access + assert_eq!(4, addr.len); + assert!(addr.offset % 4 == 0); + assert!(mask.iter().all(|&x| x)); + + let data: &[u8; 4] = data.try_into().unwrap(); + let value = u32::from_le_bytes(*data); + self.reg_write(addr.offset, value); + } +} + pub struct RegularMemory { data: Vec, } @@ -148,21 +194,28 @@ impl AddressSpace { /// Memory map: /// - 0x0400_0000 - 0x0600_0000 : framebuffer +/// - 0x4000_0000 - 0x4000_1000 : simctrl /// - 0x2000_0000 - 0xc000_0000 : ddr /// - 0xc000_0000 - 0xc040_0000 : sram -pub fn create_emu_addrspace() -> AddressSpace { +/// TODO: simctrl is inside ddr, move it elsewhere +pub fn create_emu_addrspace() -> (AddressSpace, ExitFlagRef) { const DDR_BASE: u32 = 0x2000_0000; const DDR_SIZE: u32 = 0xa000_0000; const SRAM_BASE: u32 = 0xc000_0000; const SRAM_SIZE: u32 = 0x0040_0000; + const SIMCTRL_BASE: u32 = 0x4000_0000; + const SIMCTRL_SIZE: u32 = 0x0000_1000; // one page const DISPLAY_BASE: u32 = 0x0400_0000; const DISPLAY_SIZE: u32 = 0x0200_0000; + let exit_flag = ExitFlagRef::new(); + let devices = vec![ + SimCtrl::new(exit_flag.clone()).with_addr(SIMCTRL_BASE, SIMCTRL_SIZE), RegularMemory::with_size(DDR_SIZE).with_addr(DDR_BASE, DDR_SIZE), RegularMemory::with_size(SRAM_SIZE).with_addr(SRAM_BASE, SRAM_SIZE), FrameBuffer::new().with_addr(DISPLAY_BASE, DISPLAY_SIZE), ]; - AddressSpace { devices } + (AddressSpace { devices }, exit_flag) } diff --git a/difftest/dpi_t1rocketemu/src/interconnect/simctrl.rs b/difftest/dpi_t1rocketemu/src/interconnect/simctrl.rs new file mode 100644 index 0000000000..b84efbaefc --- /dev/null +++ b/difftest/dpi_t1rocketemu/src/interconnect/simctrl.rs @@ -0,0 +1,60 @@ +use std::sync::{ + atomic::{AtomicU32, Ordering}, + Arc, +}; + +use tracing::{info, warn}; + +use super::RegDevice; + +#[derive(Default, Debug, Clone)] +pub struct ExitFlagRef(Arc); + +impl ExitFlagRef { + pub fn new() -> Self { + Self::default() + } + + pub fn is_finish(&self) -> bool { + self.0.load(Ordering::Acquire) != 0 + } + + pub fn mark_finish(&self) { + self.0.store(1, Ordering::Release); + } +} + +pub const EXIT_CODE: u32 = 0xdead_beef; + +/// Reg map: +/// - 0x0000 : WO, write EXIT_CODE to mark simulation finish +pub struct SimCtrl { + exit_flag: ExitFlagRef, +} + +impl SimCtrl { + pub fn new(exit_flag: ExitFlagRef) -> Self { + SimCtrl { exit_flag } + } +} + +impl RegDevice for SimCtrl { + fn reg_read(&mut self, offset: u32) -> u32 { + let _ = offset; + unimplemented!() + } + + fn reg_write(&mut self, reg_offset: u32, value: u32) { + match reg_offset { + 0 => { + if value == EXIT_CODE { + self.exit_flag.mark_finish(); + info!("simctrl: write EXIT_POS with EXIT_CODE, ready to quit"); + } else { + warn!("simctrl: write EXIT_POS with value 0x{value:08x}, ignored"); + } + } + _ => panic!(), + } + } +} diff --git a/difftest/dpi_t1rocketemu/src/lib.rs b/difftest/dpi_t1rocketemu/src/lib.rs index 447f4a03d8..e1016145c8 100644 --- a/difftest/dpi_t1rocketemu/src/lib.rs +++ b/difftest/dpi_t1rocketemu/src/lib.rs @@ -32,10 +32,6 @@ impl OnlineArgs { } } -// quit signal -pub const EXIT_POS: u32 = 0x4000_0000; -pub const EXIT_CODE: u32 = 0xdead_beef; - // keep in sync with TestBench.ClockGen // the value is measured in simulation time unit pub const CYCLE_PERIOD: u64 = 20000; From 95bfb1e0e8a2c67ae2d5a8b53e24340ae7204d3c Mon Sep 17 00:00:00 2001 From: Shupei Fan Date: Tue, 26 Nov 2024 16:06:15 +0000 Subject: [PATCH 08/11] [difftest & tests] move EXIT_POS to mmio space (0x40000000 -> 0x10000000) --- difftest/dpi_t1rocketemu/src/interconnect.rs | 7 +++---- difftest/spike_rs/src/spike_event.rs | 4 ++-- tests/codegen/include/riscv_test.h | 2 +- tests/emurt/emurt.c | 2 +- tests/riscv-test-env/p/riscv_test.h | 2 +- tests/t1_main.S | 2 +- 6 files changed, 9 insertions(+), 10 deletions(-) diff --git a/difftest/dpi_t1rocketemu/src/interconnect.rs b/difftest/dpi_t1rocketemu/src/interconnect.rs index ee65650f27..363e5e7bb8 100644 --- a/difftest/dpi_t1rocketemu/src/interconnect.rs +++ b/difftest/dpi_t1rocketemu/src/interconnect.rs @@ -194,17 +194,16 @@ impl AddressSpace { /// Memory map: /// - 0x0400_0000 - 0x0600_0000 : framebuffer -/// - 0x4000_0000 - 0x4000_1000 : simctrl +/// - 0x1000_0000 - 0x1000_1000 : simctrl /// - 0x2000_0000 - 0xc000_0000 : ddr /// - 0xc000_0000 - 0xc040_0000 : sram -/// TODO: simctrl is inside ddr, move it elsewhere pub fn create_emu_addrspace() -> (AddressSpace, ExitFlagRef) { const DDR_BASE: u32 = 0x2000_0000; const DDR_SIZE: u32 = 0xa000_0000; const SRAM_BASE: u32 = 0xc000_0000; const SRAM_SIZE: u32 = 0x0040_0000; - const SIMCTRL_BASE: u32 = 0x4000_0000; + const SIMCTRL_BASE: u32 = 0x1000_0000; const SIMCTRL_SIZE: u32 = 0x0000_1000; // one page const DISPLAY_BASE: u32 = 0x0400_0000; const DISPLAY_SIZE: u32 = 0x0200_0000; @@ -212,10 +211,10 @@ pub fn create_emu_addrspace() -> (AddressSpace, ExitFlagRef) { let exit_flag = ExitFlagRef::new(); let devices = vec![ - SimCtrl::new(exit_flag.clone()).with_addr(SIMCTRL_BASE, SIMCTRL_SIZE), RegularMemory::with_size(DDR_SIZE).with_addr(DDR_BASE, DDR_SIZE), RegularMemory::with_size(SRAM_SIZE).with_addr(SRAM_BASE, SRAM_SIZE), FrameBuffer::new().with_addr(DISPLAY_BASE, DISPLAY_SIZE), + SimCtrl::new(exit_flag.clone()).with_addr(SIMCTRL_BASE, SIMCTRL_SIZE), ]; (AddressSpace { devices }, exit_flag) } diff --git a/difftest/spike_rs/src/spike_event.rs b/difftest/spike_rs/src/spike_event.rs index e05039bea4..b36cd1c5c0 100644 --- a/difftest/spike_rs/src/spike_event.rs +++ b/difftest/spike_rs/src/spike_event.rs @@ -460,8 +460,8 @@ impl SpikeEvent { }); trace!("SpikeMemWrite: addr={addr:x}, value={value:x}, size={size}"); - if addr == 0x4000_0000 && value == 0xdead_beef { - trace!("SpikeExit: exit by writing 0xdeadbeef to 0x40000000"); + if addr == 0x1000_0000 && value == 0xdead_beef { + trace!("SpikeExit: exit by writing 0xdeadbeef to 0x10000000"); self.is_exit = true; return; diff --git a/tests/codegen/include/riscv_test.h b/tests/codegen/include/riscv_test.h index cb0d21863b..05ae7111df 100644 --- a/tests/codegen/include/riscv_test.h +++ b/tests/codegen/include/riscv_test.h @@ -157,7 +157,7 @@ // Write our custom CSR msimend to exit simulation. #define RVTEST_CODE_END \ - li x1, 0x40000000; \ + li x1, 0x10000000; \ li x2, 0xdeadbeef; \ sw x2, 0(x1); \ j .; diff --git a/tests/emurt/emurt.c b/tests/emurt/emurt.c index 01fc670ef1..04fd1b4166 100644 --- a/tests/emurt/emurt.c +++ b/tests/emurt/emurt.c @@ -54,7 +54,7 @@ int _write(int file, char* ptr, int len) { } void _exit(int code) { - __asm__("li x1, 0x40000000"); + __asm__("li x1, 0x10000000"); __asm__("li x2, 0xdeadbeef"); __asm__("sw x2, 0(x1)"); __asm__("j ."); diff --git a/tests/riscv-test-env/p/riscv_test.h b/tests/riscv-test-env/p/riscv_test.h index 3bab9ce13c..00dc5b95aa 100644 --- a/tests/riscv-test-env/p/riscv_test.h +++ b/tests/riscv-test-env/p/riscv_test.h @@ -237,7 +237,7 @@ reset_vector: \ // End Macro //----------------------------------------------------------------------- -#define EXIT_POS 0x40000000; +#define EXIT_POS 0x10000000; #define EXIT_CODE 0xdeadbeef; #define RVTEST_CODE_END \ li x1, EXIT_POS; \ diff --git a/tests/t1_main.S b/tests/t1_main.S index 1fa0815768..18151c8635 100644 --- a/tests/t1_main.S +++ b/tests/t1_main.S @@ -10,7 +10,7 @@ _start: call test // exit - li x1, 0x40000000 + li x1, 0x10000000 li x2, 0xdeadbeef sw x2, 0(x1) j . From 3a4cb1b2b39f0338cdd63f8f694f142c664b518a Mon Sep 17 00:00:00 2001 From: Avimitin Date: Mon, 18 Nov 2024 17:08:28 +0800 Subject: [PATCH 09/11] [tests] initialize all scalar register to zero Signed-off-by: Avimitin --- tests/t1_main.S | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tests/t1_main.S b/tests/t1_main.S index 18151c8635..c0400f4671 100644 --- a/tests/t1_main.S +++ b/tests/t1_main.S @@ -4,6 +4,38 @@ _start: csrs mstatus, a0 csrwi vcsr, 0 + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + la sp, __stacktop // no ra to save From 6328ee51d31ad9850da067d54ca9dd8baf070af0 Mon Sep 17 00:00:00 2001 From: github-actions Date: Thu, 28 Nov 2024 07:22:41 +0000 Subject: [PATCH 10/11] [ci] update t1 test case cycle data --- .github/designs/blastoise/t1rocketemu.json | 62 +++++++++++----------- .github/designs/rookidee/t1rocketemu.json | 34 ++++++------ 2 files changed, 48 insertions(+), 48 deletions(-) diff --git a/.github/designs/blastoise/t1rocketemu.json b/.github/designs/blastoise/t1rocketemu.json index 642fe75887..c2b439f443 100644 --- a/.github/designs/blastoise/t1rocketemu.json +++ b/.github/designs/blastoise/t1rocketemu.json @@ -1,9 +1,9 @@ { - "asm.memcpy": 751, - "asm.mmm": 51782, - "asm.smoke": 7524, - "asm.strlen": 7989, - "asm.utf8_count": 206, + "asm.memcpy": 774, + "asm.mmm": 51827, + "asm.smoke": 7574, + "asm.strlen": 8012, + "asm.utf8_count": 233, "codegen.vaadd_vv": 170268, "codegen.vaadd_vx": 560487, "codegen.vaaddu_vv": 170268, @@ -499,30 +499,30 @@ "codegen.vxor_vx": 141561, "codegen.vzext_vf2": 14022, "codegen.vzext_vf4": 4335, - "intrinsic.conv2d_less_m2": 2498, - "intrinsic.linear_normalization": 3347, - "intrinsic.matmul": 60391, - "intrinsic.softmax": 6744, - "mlir.axpy_masked": 4179, - "mlir.conv": 125860, - "mlir.hello": 131, - "mlir.matmul": 56060, - "mlir.maxvl_tail_setvl_front": 694, - "mlir.rvv_vp_intrinsic_add": 471, - "mlir.rvv_vp_intrinsic_add_scalable": 813, - "mlir.stripmining": 8883, - "mlir.vectoradd": 13237, - "pytorch.demo": 31521, - "pytorch.matmul": 69795, - "rvv_bench.ascii_to_utf16": 677102, - "rvv_bench.ascii_to_utf32": 226944, - "rvv_bench.byteswap": 400174, - "rvv_bench.chacha20": 39957, - "rvv_bench.mandelbrot": 519965, - "rvv_bench.memcpy": 671957, - "rvv_bench.memset": 290725, - "rvv_bench.mergelines": 564312, - "rvv_bench.poly1305": 39957, - "rvv_bench.strlen": 219194, - "rvv_bench.utf8_count": 2285456 + "intrinsic.conv2d_less_m2": 2527, + "intrinsic.linear_normalization": 3370, + "intrinsic.matmul": 60420, + "intrinsic.softmax": 6773, + "mlir.axpy_masked": 4229, + "mlir.conv": 125882, + "mlir.hello": 175, + "mlir.matmul": 56110, + "mlir.maxvl_tail_setvl_front": 743, + "mlir.rvv_vp_intrinsic_add": 522, + "mlir.rvv_vp_intrinsic_add_scalable": 864, + "mlir.stripmining": 8932, + "mlir.vectoradd": 13282, + "pytorch.demo": 31524, + "pytorch.matmul": 69837, + "rvv_bench.ascii_to_utf16": 677008, + "rvv_bench.ascii_to_utf32": 226957, + "rvv_bench.byteswap": 400180, + "rvv_bench.chacha20": 40010, + "rvv_bench.mandelbrot": 520000, + "rvv_bench.memcpy": 671671, + "rvv_bench.memset": 290750, + "rvv_bench.mergelines": 564457, + "rvv_bench.poly1305": 40010, + "rvv_bench.strlen": 219233, + "rvv_bench.utf8_count": 2285480 } \ No newline at end of file diff --git a/.github/designs/rookidee/t1rocketemu.json b/.github/designs/rookidee/t1rocketemu.json index 588881f09d..cd48bae70f 100644 --- a/.github/designs/rookidee/t1rocketemu.json +++ b/.github/designs/rookidee/t1rocketemu.json @@ -1,6 +1,6 @@ { - "asm.mmm": 56295, - "asm.smoke": 7780, + "asm.mmm": 56340, + "asm.smoke": 7830, "codegen.vaadd_vv": 129499, "codegen.vaadd_vx": 393229, "codegen.vaaddu_vv": 129499, @@ -430,19 +430,19 @@ "codegen.vxor_vx": 98738, "codegen.vzext_vf2": 11522, "codegen.vzext_vf4": 3497, - "intrinsic.conv2d_less_m2": 2540, - "mlir.hello": 130, - "mlir.rvv_vp_intrinsic_add": 462, - "mlir.rvv_vp_intrinsic_add_scalable": 706, - "mlir.stripmining": 27825, - "rvv_bench.ascii_to_utf16": 678943, - "rvv_bench.ascii_to_utf32": 226997, - "rvv_bench.byteswap": 422035, - "rvv_bench.chacha20": 39957, - "rvv_bench.memcpy": 677231, - "rvv_bench.memset": 295653, - "rvv_bench.mergelines": 580218, - "rvv_bench.poly1305": 39957, - "rvv_bench.strlen": 235252, - "rvv_bench.utf8_count": 2346912 + "intrinsic.conv2d_less_m2": 2569, + "mlir.hello": 174, + "mlir.rvv_vp_intrinsic_add": 513, + "mlir.rvv_vp_intrinsic_add_scalable": 757, + "mlir.stripmining": 27874, + "rvv_bench.ascii_to_utf16": 678815, + "rvv_bench.ascii_to_utf32": 227043, + "rvv_bench.byteswap": 422055, + "rvv_bench.chacha20": 40010, + "rvv_bench.memcpy": 676973, + "rvv_bench.memset": 295675, + "rvv_bench.mergelines": 580383, + "rvv_bench.poly1305": 40010, + "rvv_bench.strlen": 235292, + "rvv_bench.utf8_count": 2346964 } \ No newline at end of file From e1dcc1dd5b21c7825cf382c6c4d8f9d7da3dcf4c Mon Sep 17 00:00:00 2001 From: Avimitin Date: Wed, 27 Nov 2024 21:35:14 +0000 Subject: [PATCH 11/11] [deps] Bump T1 dependencies --- nix/t1/dependencies/_sources/generated.json | 6 +++--- nix/t1/dependencies/_sources/generated.nix | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/nix/t1/dependencies/_sources/generated.json b/nix/t1/dependencies/_sources/generated.json index cf3323d5fd..fd15a84aab 100644 --- a/nix/t1/dependencies/_sources/generated.json +++ b/nix/t1/dependencies/_sources/generated.json @@ -53,11 +53,11 @@ "name": null, "owner": "chipsalliance", "repo": "chisel", - "rev": "118502e5683430610911d8ddae21363c3e06ec01", - "sha256": "sha256-XeqlDmw5ojM8EUYKAi3kTVYX37DB6ZbiHb1rb56dg3w=", + "rev": "892fa8020aa329274a85f782b252cad6a32a9f4d", + "sha256": "sha256-+uGGThfIYiQtbXARj1FThCowh07kNwmxbhaZhkKhoL4=", "type": "github" }, - "version": "118502e5683430610911d8ddae21363c3e06ec01" + "version": "892fa8020aa329274a85f782b252cad6a32a9f4d" }, "chisel-interface": { "cargoLocks": null, diff --git a/nix/t1/dependencies/_sources/generated.nix b/nix/t1/dependencies/_sources/generated.nix index bb1c3c02df..fd2bc5cfa2 100644 --- a/nix/t1/dependencies/_sources/generated.nix +++ b/nix/t1/dependencies/_sources/generated.nix @@ -27,13 +27,13 @@ }; chisel = { pname = "chisel"; - version = "118502e5683430610911d8ddae21363c3e06ec01"; + version = "892fa8020aa329274a85f782b252cad6a32a9f4d"; src = fetchFromGitHub { owner = "chipsalliance"; repo = "chisel"; - rev = "118502e5683430610911d8ddae21363c3e06ec01"; + rev = "892fa8020aa329274a85f782b252cad6a32a9f4d"; fetchSubmodules = false; - sha256 = "sha256-XeqlDmw5ojM8EUYKAi3kTVYX37DB6ZbiHb1rb56dg3w="; + sha256 = "sha256-+uGGThfIYiQtbXARj1FThCowh07kNwmxbhaZhkKhoL4="; }; date = "2024-11-26"; };