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prevent formatter from adding space between 'if' and '(' ? #2345

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gobbedy opened this issue Jan 30, 2025 · 0 comments
Open

prevent formatter from adding space between 'if' and '(' ? #2345

gobbedy opened this issue Jan 30, 2025 · 0 comments
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formatter Verilog code formatter issues

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@gobbedy
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gobbedy commented Jan 30, 2025

Hello,

I noticed that the formatter adds a space between any 'if' and the subsequent parathensis, ie '('.

Can we get an option to prevent this from happening? Sorry if I missed such an option if it already exists..

Thanks in advance!

Test case

class my_class;
    function void my_func();
        if(1)
            $display("do something");
    endfunction
endclass

Actual output

class my_class;
    function void my_func();
        if (1) // <--- SPACE ADDED ON THIS LINE
            $display("do something");
    endfunction
endclass
@gobbedy gobbedy added the formatter Verilog code formatter issues label Jan 30, 2025
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Labels
formatter Verilog code formatter issues
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