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Interface class formatting #2347

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Sladkoeshechka opened this issue Jan 31, 2025 · 0 comments
Open

Interface class formatting #2347

Sladkoeshechka opened this issue Jan 31, 2025 · 0 comments
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formatter Verilog code formatter issues

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@Sladkoeshechka
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Test case

interface class verifiable;
  pure virtual function void assert_is_correct();
  pure virtual function bit is_correct();
endclass

Include any options or configuration used.

--column_limit=120
--indentation_spaces=2
--assignment_statement_alignment=infer
--case_items_alignment=infer
--compact_indexing_and_selections=true
--distribution_items_alignment=infer
--enum_assignment_statement_alignment=infer
--expand_coverpoints=true
--formal_parameters_alignment=infer
--formal_parameters_indentation=indent
--module_net_variable_alignment=infer
--named_parameter_alignment=infer
--named_parameter_indentation=indent
--named_port_alignment=infer
--named_port_indentation=indent
--port_declarations_alignment=infer
--port_declarations_indentation=indent
--port_declarations_right_align_packed_dimensions=true
--port_declarations_right_align_unpacked_dimensions=true
--struct_union_members_alignment=infer
--wrap_end_else_clauses=true

Actual output

  interface class verifiable; pure virtual
  function void assert_is_correct()
  ; pure virtual
  function bit is_correct()
  ;
  endclass

Include any possible diagnostic messages from the formatter.

Expected or suggested output

interface class verifiable;
  pure virtual function void assert_is_correct();
  pure virtual function bit is_correct();
endclass

Citations to published style guides would help.

@Sladkoeshechka Sladkoeshechka added the formatter Verilog code formatter issues label Jan 31, 2025
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Labels
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