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Commit fd3faa4

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author
Navid Jafarof
committed
Changed pass, added the synplify map file, and edited makefile
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3 files changed

+352
-233
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3 files changed

+352
-233
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ql-qlf-plugin/Makefile

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@@ -68,6 +68,7 @@ VERILOG_MODULES = $(COMMON)/cells_sim.v \
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$(QLF_K6N10F_DIR)/dsp_final_map.v \
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$(QLF_K6N10F_DIR)/libmap_brams_map_tdp.v \
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$(QLF_K6N10F_DIR)/libmap_brams_map_sdp.v \
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$(QLF_K6N10F_DIR)/synplify_map.v \
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$(QLF_K6N10F_DIR)/libmap_brams_sdp.txt \
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$(QLF_K6N10F_DIR)/libmap_brams_tdp.txt \
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$(PP3_DIR)/abc9_map.v \
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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\$lut #(
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.WIDTH(1),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A(I0),
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.Y(O)
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);
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endmodule
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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\$lut #(
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.WIDTH(2),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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\$lut #(
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.WIDTH(3),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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\$lut #(
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.WIDTH(4),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I3, I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT5(output O, input I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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\$lut #(
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.WIDTH(5),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I4, I3, I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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\$lut #(
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.WIDTH(6),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I5, I4, I3, I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module VCC(output P);
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assign P = 1;
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endmodule
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module GND(output G);
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assign G = 0;
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endmodule
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