Backend implementation

Each processor architecture supported by Chez Scheme has a corresponding backend file. For example, s/x86_64.ss implements the x86_64 backend used by, e.g., a64le, ta64le, a6osx, and a6nt. While other parts of Chez Scheme have different code for different architectures, the backend files contain the vast majority of the architecture-specific code. When adding support for a new architecture to Chez Scheme, implementing the corresponding backend file comprises the bulk of the work to do so.

Chez Scheme backend files consist of three logical sections:

1. Register declarations
2. Instruction definitions
3. Assembler definitions

Section 1: Register Declarations

The first section, register declarations, specifies what registers are available for a given architecture and how Chez Scheme can use them. It is also the shortest and easiest to implement of the three, since it consists solely of a call to the define-registers macro (defined in cpnanopass.ss).

By way of example, here is the define-registers from arm32.ss as of Chez Scheme v9.5.6:

(define-registers
  (reserved
    [%tc  %r9                   #t  9]
    [%sfp %r10                  #t 10]
    [%ap  %r5                   #t  5]
    #;[%esp]
    #;[%eap]
    [%trap %r8                  #t  8])
  (allocable
    [%ac0 %r4                   #t  4]
    [%xp  %r6                   #t  6]
    [%ts  %ip                   #f 12]
    [%td  %r11                  #t 11]
    #;[%ret]
    [%cp  %r7                   #t  7]
    #;[%ac1]
    #;[%yp]
    [     %r0  %Carg1 %Cretval  #f  0]
    [     %r1  %Carg2           #f  1]
    [     %r2  %Carg3           #f  2]
    [     %r3  %Carg4           #f  3]
    [     %lr                   #f 14] ; %lr is trashed by 'c' calls including calls to hand-coded routines like get-room
  )
  (machine-dependent
    [%sp                        #t 13]
    [%pc                        #f 15]
    [%Cfparg1 %Cfpretval %d0  %s0   #f  0] ; < 32: low bit goes in D, N, or M bit, high bits go in Vd, Vn, Vm
    [%Cfparg1b                %s1   #f  1]
    [%Cfparg2            %d1  %s2   #f  2]
    [%Cfparg2b                %s3   #f  3]
    [%Cfparg3            %d2  %s4   #f  4]
    [%Cfparg3b                %s5   #f  5]
    [%Cfparg4            %d3  %s6   #f  6]
    [%Cfparg4b                %s7   #f  7]
    [%Cfparg5            %d4  %s8   #f  8]
    [%Cfparg5b                %s9   #f  9]
    [%Cfparg6            %d5  %s10  #f 10]
    [%Cfparg6b                %s11  #f 11]
    [%Cfparg7            %d6  %s12  #f 12]
    [%Cfparg7b                %s13  #f 13]
    [%Cfparg8            %d7  %s14  #f 14]
    [%Cfparg8b                %s15  #f 15]
    [%flreg1             %d8  %s16  #f 16]
    [%flreg2             %d9  %s18  #f 18]
    ; etc.
    #;[                  %d16       #f 32] ; >= 32: high bit goes in D, N, or M bit, low bits go in Vd, Vn, Vm
    #;[                  %d17       #f 33]
    ; etc.
    ))