Add wishbone fifo's

[christiaanb]

Add the following circuits:

-- | Wishbone to Df source 
-- 
-- * Writing to the given address, pushes an item onto the fifo
-- * Reading always returns zero
-- * Writing to other addresses are acknowledged, but ignored
-- * Asserts stall when the FIFO is full
wishboneSource ::
  -- | Address to respond to
  BitVector addressWidth ->
  -- | Depth of the FIFO
  SNat depth
  -- |
  (Signal dom (WishboneM2S bytes), Signal dom Ack) ->
  -- |
  (Signal dom (WisboneS2M bytes addressWidth, Signal dom (Data (BitVector (8 * bytes)))

-- | Wishbone to Df sink
--
-- * Reading from the given address, pops an item from the fifo
-- * Writes are acknowledged, but ignored
-- * Reads from any other address are acknowledged, but the fifo element is not popped.
-- * Asserts stall when the FIFO is empty
wishboneSink :: 
  -- | Address to respond to
  BitVector addressWidth ->
  -- | Depth of the FIFO
  SNat depth
  -- | 
  (Signal dom (WishboneM2S bytes), Signal dom (Data (BitVector (8 * bytes))) ->
  -- |
  (Signal dom (WisboneS2M bytes addressWidth, Signal dom Ack)