@@ -41,7 +41,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
4141
4242 /* XXX: restore cpu registers saved in host registers */
4343
44- env -> exception_index = -1 ;
44+ cpu -> exception_index = -1 ;
4545 siglongjmp (cpu -> jmp_env , 1 );
4646}
4747#endif
@@ -282,16 +282,16 @@ int cpu_exec(CPUArchState *env)
282282#else
283283#error unsupported target CPU
284284#endif
285- env -> exception_index = -1 ;
285+ cpu -> exception_index = -1 ;
286286
287287 /* prepare setjmp context for exception handling */
288288 for (;;) {
289289 if (sigsetjmp (cpu -> jmp_env , 0 ) == 0 ) {
290290 /* if an exception is pending, we execute it here */
291- if (env -> exception_index >= 0 ) {
292- if (env -> exception_index >= EXCP_INTERRUPT ) {
291+ if (cpu -> exception_index >= 0 ) {
292+ if (cpu -> exception_index >= EXCP_INTERRUPT ) {
293293 /* exit request from the cpu execution loop */
294- ret = env -> exception_index ;
294+ ret = cpu -> exception_index ;
295295 if (ret == EXCP_DEBUG ) {
296296 cpu_handle_debug_exception (env );
297297 }
@@ -304,11 +304,11 @@ int cpu_exec(CPUArchState *env)
304304#if defined(TARGET_I386 )
305305 cc -> do_interrupt (cpu );
306306#endif
307- ret = env -> exception_index ;
307+ ret = cpu -> exception_index ;
308308 break ;
309309#else
310310 cc -> do_interrupt (cpu );
311- env -> exception_index = -1 ;
311+ cpu -> exception_index = -1 ;
312312#endif
313313 }
314314 }
@@ -323,7 +323,7 @@ int cpu_exec(CPUArchState *env)
323323 }
324324 if (interrupt_request & CPU_INTERRUPT_DEBUG ) {
325325 cpu -> interrupt_request &= ~CPU_INTERRUPT_DEBUG ;
326- env -> exception_index = EXCP_DEBUG ;
326+ cpu -> exception_index = EXCP_DEBUG ;
327327 cpu_loop_exit (env );
328328 }
329329#if defined(TARGET_ARM ) || defined(TARGET_SPARC ) || defined(TARGET_MIPS ) || \
@@ -332,7 +332,7 @@ int cpu_exec(CPUArchState *env)
332332 if (interrupt_request & CPU_INTERRUPT_HALT ) {
333333 cpu -> interrupt_request &= ~CPU_INTERRUPT_HALT ;
334334 cpu -> halted = 1 ;
335- env -> exception_index = EXCP_HLT ;
335+ cpu -> exception_index = EXCP_HLT ;
336336 cpu_loop_exit (env );
337337 }
338338#endif
@@ -347,7 +347,7 @@ int cpu_exec(CPUArchState *env)
347347 cpu_svm_check_intercept_param (env , SVM_EXIT_INIT ,
348348 0 );
349349 do_cpu_init (x86_cpu );
350- env -> exception_index = EXCP_HALTED ;
350+ cpu -> exception_index = EXCP_HALTED ;
351351 cpu_loop_exit (env );
352352 } else if (interrupt_request & CPU_INTERRUPT_SIPI ) {
353353 do_cpu_sipi (x86_cpu );
@@ -419,7 +419,7 @@ int cpu_exec(CPUArchState *env)
419419#elif defined(TARGET_LM32 )
420420 if ((interrupt_request & CPU_INTERRUPT_HARD )
421421 && (env -> ie & IE_IE )) {
422- env -> exception_index = EXCP_IRQ ;
422+ cpu -> exception_index = EXCP_IRQ ;
423423 cc -> do_interrupt (cpu );
424424 next_tb = 0 ;
425425 }
@@ -428,15 +428,15 @@ int cpu_exec(CPUArchState *env)
428428 && (env -> sregs [SR_MSR ] & MSR_IE )
429429 && !(env -> sregs [SR_MSR ] & (MSR_EIP | MSR_BIP ))
430430 && !(env -> iflags & (D_FLAG | IMM_FLAG ))) {
431- env -> exception_index = EXCP_IRQ ;
431+ cpu -> exception_index = EXCP_IRQ ;
432432 cc -> do_interrupt (cpu );
433433 next_tb = 0 ;
434434 }
435435#elif defined(TARGET_MIPS )
436436 if ((interrupt_request & CPU_INTERRUPT_HARD ) &&
437437 cpu_mips_hw_interrupts_pending (env )) {
438438 /* Raise it */
439- env -> exception_index = EXCP_EXT_INTERRUPT ;
439+ cpu -> exception_index = EXCP_EXT_INTERRUPT ;
440440 env -> error_code = 0 ;
441441 cc -> do_interrupt (cpu );
442442 next_tb = 0 ;
@@ -453,7 +453,7 @@ int cpu_exec(CPUArchState *env)
453453 idx = EXCP_TICK ;
454454 }
455455 if (idx >= 0 ) {
456- env -> exception_index = idx ;
456+ cpu -> exception_index = idx ;
457457 cc -> do_interrupt (cpu );
458458 next_tb = 0 ;
459459 }
@@ -468,7 +468,7 @@ int cpu_exec(CPUArchState *env)
468468 if (((type == TT_EXTINT ) &&
469469 cpu_pil_allowed (env , pil )) ||
470470 type != TT_EXTINT ) {
471- env -> exception_index = env -> interrupt_index ;
471+ cpu -> exception_index = env -> interrupt_index ;
472472 cc -> do_interrupt (cpu );
473473 next_tb = 0 ;
474474 }
@@ -477,7 +477,7 @@ int cpu_exec(CPUArchState *env)
477477#elif defined(TARGET_ARM )
478478 if (interrupt_request & CPU_INTERRUPT_FIQ
479479 && !(env -> daif & PSTATE_F )) {
480- env -> exception_index = EXCP_FIQ ;
480+ cpu -> exception_index = EXCP_FIQ ;
481481 cc -> do_interrupt (cpu );
482482 next_tb = 0 ;
483483 }
@@ -493,14 +493,14 @@ int cpu_exec(CPUArchState *env)
493493 if (interrupt_request & CPU_INTERRUPT_HARD
494494 && ((IS_M (env ) && env -> regs [15 ] < 0xfffffff0 )
495495 || !(env -> daif & PSTATE_I ))) {
496- env -> exception_index = EXCP_IRQ ;
496+ cpu -> exception_index = EXCP_IRQ ;
497497 cc -> do_interrupt (cpu );
498498 next_tb = 0 ;
499499 }
500500#elif defined(TARGET_UNICORE32 )
501501 if (interrupt_request & CPU_INTERRUPT_HARD
502502 && !(env -> uncached_asr & ASR_I )) {
503- env -> exception_index = UC32_EXCP_INTR ;
503+ cpu -> exception_index = UC32_EXCP_INTR ;
504504 cc -> do_interrupt (cpu );
505505 next_tb = 0 ;
506506 }
@@ -535,7 +535,7 @@ int cpu_exec(CPUArchState *env)
535535 }
536536 }
537537 if (idx >= 0 ) {
538- env -> exception_index = idx ;
538+ cpu -> exception_index = idx ;
539539 env -> error_code = 0 ;
540540 cc -> do_interrupt (cpu );
541541 next_tb = 0 ;
@@ -545,7 +545,7 @@ int cpu_exec(CPUArchState *env)
545545 if (interrupt_request & CPU_INTERRUPT_HARD
546546 && (env -> pregs [PR_CCS ] & I_FLAG )
547547 && !env -> locked_irq ) {
548- env -> exception_index = EXCP_IRQ ;
548+ cpu -> exception_index = EXCP_IRQ ;
549549 cc -> do_interrupt (cpu );
550550 next_tb = 0 ;
551551 }
@@ -557,7 +557,7 @@ int cpu_exec(CPUArchState *env)
557557 m_flag_archval = M_FLAG_V32 ;
558558 }
559559 if ((env -> pregs [PR_CCS ] & m_flag_archval )) {
560- env -> exception_index = EXCP_NMI ;
560+ cpu -> exception_index = EXCP_NMI ;
561561 cc -> do_interrupt (cpu );
562562 next_tb = 0 ;
563563 }
@@ -571,7 +571,7 @@ int cpu_exec(CPUArchState *env)
571571 hardware doesn't rely on this, so we
572572 provide/save the vector when the interrupt is
573573 first signalled. */
574- env -> exception_index = env -> pending_vector ;
574+ cpu -> exception_index = env -> pending_vector ;
575575 do_interrupt_m68k_hardirq (env );
576576 next_tb = 0 ;
577577 }
@@ -583,7 +583,7 @@ int cpu_exec(CPUArchState *env)
583583 }
584584#elif defined(TARGET_XTENSA )
585585 if (interrupt_request & CPU_INTERRUPT_HARD ) {
586- env -> exception_index = EXC_IRQ ;
586+ cpu -> exception_index = EXC_IRQ ;
587587 cc -> do_interrupt (cpu );
588588 next_tb = 0 ;
589589 }
@@ -599,7 +599,7 @@ int cpu_exec(CPUArchState *env)
599599 }
600600 if (unlikely (cpu -> exit_request )) {
601601 cpu -> exit_request = 0 ;
602- env -> exception_index = EXCP_INTERRUPT ;
602+ cpu -> exception_index = EXCP_INTERRUPT ;
603603 cpu_loop_exit (env );
604604 }
605605 spin_lock (& tcg_ctx .tb_ctx .tb_lock );
@@ -669,7 +669,7 @@ int cpu_exec(CPUArchState *env)
669669 /* Execute remaining instructions. */
670670 cpu_exec_nocache (env , insns_left , tb );
671671 }
672- env -> exception_index = EXCP_INTERRUPT ;
672+ cpu -> exception_index = EXCP_INTERRUPT ;
673673 next_tb = 0 ;
674674 cpu_loop_exit (env );
675675 }
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