Merge pull request #39 from codeplaysoftware/merge-project-add-autosar-video

Add AUTOSAR Video and Merge Project

Author: scottstraughan

content/news/2023/2023-02-24-hipsycl-becomes-open-sycl-for-targeting-all-major-cpus-gpus.md

@@ -4,7 +4,6 @@ date: '2023-02-24T08:57:40.423000+00:00'
 external_url: https://www.phoronix.com/news/hipSYCL-Becomes-Open-SYCL
 image: ../../../static/images/news/2023-02-24-hipsycl-becomes-open-sycl-for-targeting-all-major-cpus-gpus.webp
 title: hipSYCL Becomes Open SYCL For Targeting All Major CPUs & GPUs
-pinned: true
 tags:
   - hipsycl
   - nvidia

content/news/2023/2023-11-13-exascale-computing-project-at-the-university-of-cambridge-uses-khronos-sycl-standard.md

@@ -4,6 +4,7 @@ date: '2023-11-13T11:20:38.571807'
 external_url: https://www.khronos.org/blog/exascale-computing-project-at-the-university-of-cambridge-uses-sycl-to-develop-performance-portable-fenics-libraries-for-the-finite-element-method
 image: ../../../static/images/news/2023-11-13-exascale-computing-project-at-the-university-of-cambridge-uses-khronos-sycl-standard.webp
 title: Exascale Computing Project at the University of Cambridge uses Khronos SYCL Standard
+pinned: true
 tags:
   - exascale
   - fenics

content/news/2024/2024-06-20-learn-sycl-in-an-hour-maybe-less.md

@@ -4,6 +4,7 @@ date: '2024-06-20T14:20:58.323249'
 external_url: https://www.intel.com/content/www/us/en/developer/articles/technical/learn-sycl-in-an-hour-maybe-less.html
 title: 'Learn SYCL* in an Hour (Maybe Less)'
 image: ../../../static/images/news/2024-06-20-learn-sycl-in-an-hour-maybe-less.webp
+pinned: true
 tags:
   - sycl
   - learning

content/news/2024/2024-06-20-uxl-foundation-and-khronos-collaborate-on-the-sycl-open-standard-for-c-programming.md

@@ -4,7 +4,6 @@ date: '2024-06-20T14:10:22.153253'
 external_url: https://www.khronos.org/blog/uxl-foundation-khronos-liaison-on-the-sycl-and-safety-critical-systems
 title: 'UXL Foundation and Khronos Collaborate on the SYCL Open Standard for C++ Programming'
 image: ../../../static/images/news/2024-06-20-uxl-foundation-and-khronos-collaborate-on-the-sycl-open-standard-for-c-programming.webp
-pinned: false
 tags:
   - edge-computing
   - performance

content/news/2024/2024-07-30-oneapi-construction-kit-4.0-brings-risc-v-host-cpu-support.md

@@ -4,6 +4,7 @@ date: '2024-07-30T14:10:22.153253'
 external_url: https://www.phoronix.com/news/oneAPI-Construction-Kit-4.0
 title: 'oneAPI Construction Kit 4.0 Brings RISC-V Host CPU Support'
 image: ../../../static/images/news/2024-07-30-oneapi-construction-kit.webp
+pinned: true
 tags:
   - oneapi
   - sycl

content/videos/2024/2022-05-27-bringing-hip-to-one-api.md renamed to content/videos/2024/2024-05-27-bringing-hip-to-one-api.md

@@ -0,0 +1,18 @@
+---
+contributor: scott
+date: '2024-08-18T00:00:00'
+title: 'Safe Hardware Accelerators Utilization In AUTOSAR AP'
+external_url: https://www.youtube.com/watch?v=VBwo-XsMv0Q
+type: presentation
+tags:
+  - autosar
+  - hardware
+  - safety
+  - adas
+  - ai
+featuring:
+  - name: Andriy Byzhynar
+    affiliation_at_video_production_time: Intellias
+---
+
+10 Intellas Safe Hardware Accelerators Utilization In AUTOSAR AP, presented by Andriy Byzhynar.

content/videos/2024/2024-08-18-10-intellas-safe-hardware-accelerators-utilization-in-autosar-ap.md

@@ -0,0 +1,30 @@
+---
+contributor: max
+date: '2025-02-02T12:11:00'
+title: 'Building Tool Chains for RISC-V AI Accelerators'
+external_url: 'https://www.youtube.com/watch?v=DqNWF26A8Io'
+type: presentation
+tags:
+  - oneapi
+  - risc-v
+featuring:
+  - name: Jeremy Bennett
+    affiliation_at_video_production_time: Embecosm
+---
+
+Building Tool Chains for RISC-V AI Accelerators - Jeremy Bennett, Embecosm
+
+Our client is developing a massively parallel 64-bit chip for AI inference workloads.
+To facilitate early software development, we are bringing up an AI tool flow for this
+chip in a QEMU RISC-V environment. In this talk, we'll share our experience of getting
+three key AI frameworks working with RISC-V QEMU: Pytorch, Tensorflow and the OpenXLA
+compiler. Our talk will share our experience addressing two key issues. We will describe
+the challenges we faced, their solutions and reflect on the lessons learned for future work.
+The first of these is simply getting the tools to effectively run in an emulated
+RISC-V environment. These tools are large, fast moving pieces of software with extensive
+external dependencies. Our second challenge is performance. AI workloads are inherently
+parallel, and hence run efficiently on vector enabled hardware. However RISC-V vector (RVV)
+is relatively new, and we experienced difficulty getting the performance we expected
+out of the tool flow. At the end of this talk, we hope our audience will have a better
+understanding of the challenges in bringing up an AI tool flow under QEMU. We hope our
+experience will help them bring up their own AI tool flows.