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cpu0.qsf
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# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# cpu0_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:01:27 AUGUST 08, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_41 -to address_bus[0]
set_location_assignment PIN_42 -to address_bus[1]
set_location_assignment PIN_43 -to address_bus[2]
set_location_assignment PIN_44 -to address_bus[3]
set_location_assignment PIN_45 -to address_bus[4]
set_location_assignment PIN_46 -to address_bus[5]
set_location_assignment PIN_47 -to address_bus[6]
set_location_assignment PIN_48 -to address_bus[7]
set_location_assignment PIN_86 -to c
set_location_assignment PIN_29 -to clk
set_location_assignment PIN_200 -to data_bus[0]
set_location_assignment PIN_201 -to data_bus[1]
set_location_assignment PIN_202 -to data_bus[2]
set_location_assignment PIN_203 -to data_bus[3]
set_location_assignment PIN_214 -to data_bus[4]
set_location_assignment PIN_215 -to data_bus[5]
set_location_assignment PIN_216 -to data_bus[6]
set_location_assignment PIN_217 -to data_bus[7]
set_location_assignment PIN_158 -to reg_data[0]
set_location_assignment PIN_159 -to reg_data[1]
set_location_assignment PIN_160 -to reg_data[2]
set_location_assignment PIN_161 -to reg_data[3]
set_location_assignment PIN_162 -to reg_data[4]
set_location_assignment PIN_163 -to reg_data[5]
set_location_assignment PIN_164 -to reg_data[6]
set_location_assignment PIN_165 -to reg_data[7]
set_location_assignment PIN_12 -to reg_sel[0]
set_location_assignment PIN_13 -to reg_sel[1]
set_location_assignment PIN_240 -to reset
set_location_assignment PIN_83 -to s
set_location_assignment PIN_16 -to sel[0]
set_location_assignment PIN_17 -to sel[1]
set_location_assignment PIN_84 -to v
set_location_assignment PIN_75 -to wr
set_location_assignment PIN_85 -to z
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE ANY
set_global_assignment -name DEVICE_FILTER_PIN_COUNT ANY
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY cpu0
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name MISC_FILE "D:/cpu/cpu0.dpf"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name MISC_FILE "F:/组成原理2022/计算机组原理实验/综合性实验/综合性实验参考材料（新）/参考材料/cpu/cpu0.dpf"
set_global_assignment -name MISC_FILE "C:/Users/Linsiri/Desktop/2024春/计算机组成/综合实验/cpu1/cpu0.dpf"
set_location_assignment PIN_14 -to write
set_global_assignment -name VHDL_FILE mux_4_to_1.vhd
set_global_assignment -name VHDL_FILE decoder_2_to_4.vhd
set_global_assignment -name VHDL_FILE asynram.vhd
set_global_assignment -name VHDL_FILE regfile.vhd
set_global_assignment -name BDF_FILE cpu0.bdf
set_global_assignment -name VHDL_FILE alu.vhd
set_global_assignment -name VHDL_FILE ar.vhd
set_global_assignment -name VHDL_FILE bus_dir.vhd
set_global_assignment -name VHDL_FILE bus_mux.vhd
set_global_assignment -name VHDL_FILE controller.vhd
set_global_assignment -name VHDL_FILE flag_reg.vhd
set_global_assignment -name VHDL_FILE ir.vhd
set_global_assignment -name VHDL_FILE pc.vhd
set_global_assignment -name VHDL_FILE reg.vhd
set_global_assignment -name VHDL_FILE reg_mux.vhd
set_global_assignment -name VHDL_FILE reg_out.vhd
set_global_assignment -name VHDL_FILE reg_test.vhd
set_global_assignment -name VHDL_FILE reg_testa.vhd
set_global_assignment -name VHDL_FILE t1.vhd
set_global_assignment -name VHDL_FILE t2.vhd
set_global_assignment -name VHDL_FILE t3.vhd
set_global_assignment -name VHDL_FILE timer.vhd