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‎alu.bsf

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 200 144)
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(text "alu" (rect 5 0 19 12)(font "Arial" ))
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(text "inst" (rect 8 112 25 124)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "cin" (rect 0 0 14 12)(font "Arial" ))
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(text "cin" (rect 21 27 35 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "alu_a[7..0]" (rect 0 0 51 12)(font "Arial" ))
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(text "alu_a[7..0]" (rect 21 43 72 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "alu_b[7..0]" (rect 0 0 51 12)(font "Arial" ))
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(text "alu_b[7..0]" (rect 21 59 72 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(pt 0 80)
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(input)
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(text "alu_func[2..0]" (rect 0 0 68 12)(font "Arial" ))
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(text "alu_func[2..0]" (rect 21 75 89 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 3))
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)
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(port
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(pt 184 32)
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(output)
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(text "alu_out[7..0]" (rect 0 0 61 12)(font "Arial" ))
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(text "alu_out[7..0]" (rect 102 27 163 39)(font "Arial" ))
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(line (pt 184 32)(pt 168 32)(line_width 3))
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)
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(port
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(pt 184 48)
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(output)
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(text "c" (rect 0 0 5 12)(font "Arial" ))
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(text "c" (rect 158 43 163 55)(font "Arial" ))
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(line (pt 184 48)(pt 168 48)(line_width 1))
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)
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(port
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(pt 184 64)
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(output)
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(text "z" (rect 0 0 4 12)(font "Arial" ))
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(text "z" (rect 159 59 163 71)(font "Arial" ))
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(line (pt 184 64)(pt 168 64)(line_width 1))
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)
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(port
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(pt 184 80)
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(output)
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(text "v" (rect 0 0 7 12)(font "Arial" ))
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(text "v" (rect 156 75 163 87)(font "Arial" ))
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(line (pt 184 80)(pt 168 80)(line_width 1))
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)
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(port
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(pt 184 96)
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(output)
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(text "s" (rect 0 0 5 12)(font "Arial" ))
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(text "s" (rect 158 91 163 103)(font "Arial" ))
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(line (pt 184 96)(pt 168 96)(line_width 1))
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)
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(drawing
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(rectangle (rect 16 16 168 112)(line_width 1))
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)
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)

‎alu.vhd

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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5+
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-- ALU Entity Declaration
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entity alu is
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port(
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cin: in std_logic; -- 进位输入
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alu_a, alu_b: in std_logic_vector(7 downto 0); -- ALU的两个输入
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alu_func: in std_logic_vector(2 downto 0); -- ALU的功能选择信号
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alu_out: out std_logic_vector(7 downto 0); -- ALU的输出
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c, z, v, s: out std_logic -- 进位、零标志、溢出标志、符号标志输出
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);
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end alu;
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-- ALU Architecture
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architecture behavioral of alu is
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signal a_in, b_in: std_logic_vector(7 downto 0);
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signal c_in: std_logic;
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signal result_add8: std_logic_vector(7 downto 0);
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signal flow_temp, co_flag: std_logic;
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component adder8bit is
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port(
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a, b: in std_logic_vector(7 downto 0);
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s: out std_logic_vector(7 downto 0);
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ci: in std_logic;
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c7, zero, overflow, negative: out std_logic
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);
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end component;
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begin
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a_in <= alu_a;
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b_in <= not alu_b when alu_func = "001" else
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"00000001" when alu_func = "010" else
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"11111110" when alu_func = "011" else
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alu_b;
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c_in <= '1' when alu_func = "001" else
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'1' when alu_func = "011" else
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'0';
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f_add: adder8bit port map(
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a => a_in,
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b => b_in,
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s => result_add8,
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ci => c_in,
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c7 => c,
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zero => z,
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overflow => v,
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negative => s
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);
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process(alu_func)
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variable f_temp: std_logic_vector(7 downto 0);
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begin
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case alu_func is
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when "000" =>
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f_temp := a_in and b_in;
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when "001" =>
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f_temp := a_in or b_in;
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when "010" =>
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f_temp := not a_in;
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when "011" =>
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f_temp := a_in xor b_in;
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when others =>
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f_temp := result_add8;
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end case;
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alu_out <= f_temp;
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end process;
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end behavioral;
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library ieee;
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use ieee.std_logic_1164.all;
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-- Adder8bit Entity Declaration
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entity adder8bit is
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port(
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a, b: in std_logic_vector(7 downto 0);
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s: out std_logic_vector(7 downto 0);
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ci: in std_logic;
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c7, zero, overflow, negative: out std_logic
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);
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end adder8bit;
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-- Adder8bit Architecture
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architecture structure of adder8bit is
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component fa is
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port(
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a, b, ci: in std_logic;
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s, co: out std_logic
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);
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end component;
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signal s_temp, c: std_logic_vector(7 downto 0);
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signal overflow_temp: std_logic;
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begin
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f0: fa port map(a => a(0), b => b(0), ci => ci, s => s_temp(0), co => c(0));
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f1_7: for i in 1 to 7 generate
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fm: fa port map(a => a(i), b => b(i), ci => c(i-1), s => s_temp(i), co => c(i));
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end generate f1_7;
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s <= s_temp;
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c7 <= c(7);
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zero <= '1' when s_temp = "00000000" else '0';
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overflow_temp <= c(7) xor c(6);
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overflow <= '1' when overflow_temp = '1' else '0';
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negative <= '1' when s_temp(7) = '1' else '0';
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end structure;
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library ieee;
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use ieee.std_logic_1164.all;
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-- FA Entity Declaration
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entity fa is
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port(
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a, b, ci: in std_logic;
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s, co: out std_logic
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);
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end fa;
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-- FA Architecture
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architecture b_fa of fa is
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begin
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s <= a xor b xor ci;
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co <= ((a xor b) and ci) or (a and b);
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end b_fa;

‎alu.vhd.bak

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- ALU Entity Declaration
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entity alu is
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port(
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cin: in std_logic; -- �����
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alu_a, alu_b: in std_logic_vector(7 downto 0); -- ALU����������
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alu_func: in std_logic_vector(2 downto 0); -- ALU�Ĺ���ѡ���ź�
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alu_out: out std_logic_vector(7 downto 0); -- ALU�����
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c, z, v, s: out std_logic -- ��λ�����־�������־�����ű�־���
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);
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end alu;
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-- ALU Architecture
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architecture behavioral of alu is
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signal a_in, b_in: std_logic_vector(7 downto 0);
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signal c_in: std_logic;
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signal result_add8: std_logic_vector(7 downto 0);
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signal flow_temp, co_flag: std_logic;
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component adder8bit is
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port(
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a, b: in std_logic_vector(7 downto 0);
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s: out std_logic_vector(7 downto 0);
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ci: in std_logic;
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c7, zero, overflow, negative: out std_logic
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);
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end component;
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begin
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a_in <= alu_a;
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b_in <= not alu_b when alu_func = "001" else
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"00000001" when alu_func = "010" else
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"11111110" when alu_func = "011" else
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alu_b;
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c_in <= '1' when alu_func = "001" else
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'1' when alu_func = "011" else
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'0';
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f_add: adder8bit port map(
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a => a_in,
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b => b_in,
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s => result_add8,
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ci => c_in,
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c7 => c,
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zero => z,
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overflow => v,
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negative => s
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);
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process(alu_func)
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variable f_temp: std_logic_vector(7 downto 0);
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begin
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case alu_func is
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when "000" =>
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f_temp := a_in and b_in;
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when "001" =>
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f_temp := a_in or b_in;
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when "010" =>
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f_temp := not a_in;
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when "011" =>
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f_temp := a_in xor b_in;
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when others =>
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f_temp := result_add8;
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end case;
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alu_out <= f_temp;
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end process;
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end behavioral;
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library ieee;
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use ieee.std_logic_1164.all;
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-- Adder8bit Entity Declaration
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entity adder8bit is
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port(
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a, b: in std_logic_vector(7 downto 0);
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s: out std_logic_vector(7 downto 0);
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ci: in std_logic;
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c7, zero, overflow, negative: out std_logic
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);
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end adder8bit;
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-- Adder8bit Architecture
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architecture structure of adder8bit is
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component fa is
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port(
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a, b, ci: in std_logic;
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s, co: out std_logic
93+
);
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end component;
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signal s_temp, c: std_logic_vector(7 downto 0);
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signal overflow_temp: std_logic;
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begin
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f0: fa port map(a => a(0), b => b(0), ci => ci, s => s_temp(0), co => c(0));
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f1_7: for i in 1 to 7 generate
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fm: fa port map(a => a(i), b => b(i), ci => c(i-1), s => s_temp(i), co => c(i));
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end generate f1_7;
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s <= s_temp;
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c7 <= c(7);
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zero <= '1' when s_temp = "00000000" else '0';
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overflow_temp <= c(7) xor c(6);
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overflow <= '1' when overflow_temp = '1' else '0';
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negative <= '1' when s_temp(7) = '1' else '0';
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end structure;
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-- FA Entity Declaration
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entity fa is
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port(
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a, b, ci: in std_logic;
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s, co: out std_logic
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);
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end fa;
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-- FA Architecture
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architecture b_fa of fa is
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begin
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s <= a xor b xor ci;
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co <= ((a xor b) and ci) or (a and b);
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end b_fa;

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