[Intel] Routing the Haswell-EP devices (initial implementation)

[SNB] Refactoring the count of IMC channels & DIMMs

Author: cyring

corefreq-api.h

@@ -657,10 +657,14 @@ typedef struct
 	/* 5008h */				MAD1;		/* 32 bits    */
 		} SNB;
 		struct {
-			SNB_EP_MC_TECH		TECH;		/* 32 bits    */
+	/* 7Ch*/	SNB_EP_MC_TECH		TECH;		/* 32 bits    */
 	/* 80h */	SNB_EP_TADWAYNESS	TAD;		/* 12x32 bits */
 		} SNB_EP;
 		struct {
+	/* 7Ch*/	HSW_EP_MC_TECH		TECH;		/* 32 bits    */
+	/* 80h */	HSW_EP_TADWAYNESS	TAD;		/* 12x32 bits */
+		} HSW_EP;
+		struct {
 	/* 5000h */	SKL_IMC_MAD_MAPPING	MADCH;		/* 32 bits    */
 	/* 5004h */	SKL_IMC_MAD_CHANNEL	MADC0,		/* 32 bits    */
 	/* 5008h */				MADC1;		/* 32 bits    */
@@ -1193,21 +1197,23 @@ typedef struct
 /*	QPIMISCSTAT: Device=8 - Function=0				*/
 #define DID_INTEL_HSW_EP_QPI_LINK0	0x2f80
 /*	Integrated Memory Controller # : General and MemHot Registers	*/
-/*	Xeon E5 - CPGC: Device=19 - Function=0				*/
-#define DID_INTEL_HSW_EP_IMC_CTRL0_CPGC 0x2fa8
-/*	Xeon E7 - CPGC: Device=22 - Function=0				*/
-#define DID_INTEL_HSW_EP_IMC_CTRL1_CPGC 0x2f68
+/*	Xeon E7 - CPGC: Device=19 - Function=0,1			*/
+#define DID_INTEL_HSW_E7_IMC_CTRL0_F0_CPGC 0x2fa8
+#define DID_INTEL_HSW_E7_IMC_CTRL0_F1_CPGC 0x2f71
+/*	Xeon E7 - CPGC: Device=22 - Function=0,1			*/
+#define DID_INTEL_HSW_E7_IMC_CTRL1_F0_CPGC 0x2f68
+#define DID_INTEL_HSW_E7_IMC_CTRL1_F1_CPGC 0x2f79
 /*	Integrated Memory Controller # : Channel [m-M] Thermal Registers*/
-/*TODO( Controller #0: Device=?? - Function=0,1,2,3 )
-#define DID_INTEL_HSW_EP_IMC_CTRL0_CH0	0x0
-#define DID_INTEL_HSW_EP_IMC_CTRL0_CH1	0x0
-#define DID_INTEL_HSW_EP_IMC_CTRL0_CH2	0x0
-#define DID_INTEL_HSW_EP_IMC_CTRL0_CH3	0x0				*/
-/*TODO( Controller #1: Device=?? - Function=4,5,6,7 )
-#define DID_INTEL_HSW_EP_IMC_CTRL1_CH0	0x0
-#define DID_INTEL_HSW_EP_IMC_CTRL1_CH1	0x0
-#define DID_INTEL_HSW_EP_IMC_CTRL1_CH2	0x0
-#define DID_INTEL_HSW_EP_IMC_CTRL1_CH3	0x0			*/
+/*	Controller #0: Device=20,21 - Function=0,1			*/
+#define DID_INTEL_HSW_EP_IMC_CTRL0_CH0	0x2fb4
+#define DID_INTEL_HSW_EP_IMC_CTRL0_CH1	0x2fb5
+#define DID_INTEL_HSW_EP_IMC_CTRL0_CH2	0x2fb0
+#define DID_INTEL_HSW_EP_IMC_CTRL0_CH3	0x2fb1
+/*	Controller #1: Device=23,24 - Function=2,3			*/
+#define DID_INTEL_HSW_EP_IMC_CTRL1_CH0	0x2fd6
+#define DID_INTEL_HSW_EP_IMC_CTRL1_CH1	0x2fd7
+#define DID_INTEL_HSW_EP_IMC_CTRL1_CH2	0x2fd2
+#define DID_INTEL_HSW_EP_IMC_CTRL1_CH3	0x2fd3
 /*	Integrated Memory Controller 0 : Channel # TAD Registers	*/
 /*	Xeon E5 - TAD Controller #0: Device=19 - Function=2,3,4,5	*/
 #define DID_INTEL_HSW_EP_TAD_CTRL0_CH0	0x2faa

corefreqd.c

@@ -3952,6 +3952,78 @@ void HSW_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	}
 }
 
+#define HSW_EP_IMC	SNB_EP_IMC
+
+void HSW_EP_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
+{
+	switch (RO(Proc)->Uncore.Bus.SNB_EP_Cap1.DMFC) {
+	case 0b111:
+		RO(Shm)->Uncore.CtrlSpeed = 1066;
+		break;
+	case 0b110:
+		RO(Shm)->Uncore.CtrlSpeed = 1333;
+		break;
+	case 0b101:
+		RO(Shm)->Uncore.CtrlSpeed = 1600;
+		break;
+	case 0b100:
+		RO(Shm)->Uncore.CtrlSpeed = 1866;
+		break;
+	case 0b011:
+		RO(Shm)->Uncore.CtrlSpeed = 2133;
+		break;
+	case 0b010:
+		RO(Shm)->Uncore.CtrlSpeed = 2400;
+		break;
+	case 0b001:
+		RO(Shm)->Uncore.CtrlSpeed = 2666;
+		break;
+	case 0b000:
+		RO(Shm)->Uncore.CtrlSpeed = 2933;
+		break;
+	}
+
+	RO(Shm)->Uncore.CtrlSpeed *= RO(Core)->Clock.Hz;
+	RO(Shm)->Uncore.CtrlSpeed /= RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+	RO(Shm)->Uncore.Bus.Rate = \
+		RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b010 ?
+	5600 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b011 ?
+	6400 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b100 ?
+	7200 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b101 ?
+	8000 :	RO(Proc)->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b111 ?
+	9600 : 6400;
+
+	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
+				* RO(Shm)->Uncore.Bus.Rate)
+				/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MTS;
+	RO(Shm)->Uncore.Unit.BusSpeed = MC_MTS;
+	RO(Shm)->Uncore.Unit.DDR_Rate = MC_NIL;
+	RO(Shm)->Uncore.Unit.DDRSpeed = MC_MHZ;
+
+	if (RO(Proc)->Uncore.MC[0].HSW_EP.TECH.DDR4_Mode) {
+		RO(Shm)->Uncore.Unit.DDR_Ver = 4;
+	} else {
+		RO(Shm)->Uncore.Unit.DDR_Ver = 3;
+	}
+	if (RO(Proc)->Uncore.Bus.SNB_EP_Cap3.RDIMM_DIS)
+	{
+		if (RO(Proc)->Uncore.Bus.SNB_EP_Cap3.UDIMM_DIS) {
+			RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_UNSPEC;
+		} else {
+			RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_SDRAM;
+		}
+	} else {
+		RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_RDIMM;
+	}
+/*TODO(VT-d capability from device 30 in CAPID# registers among offsets 0x80)*/
+	RO(Shm)->Proc.Technology.IOMMU = 0;
+	RO(Shm)->Proc.Technology.IOMMU_Ver_Major = 0;
+	RO(Shm)->Proc.Technology.IOMMU_Ver_Minor = 0;
+}
+
 unsigned int SKL_DimmWidthToRows(unsigned int width)
 {
 	unsigned int rows = 0;
@@ -5822,6 +5894,11 @@ void PCI_Intel(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core),
 		HSW_IMC(RO(Shm), RO(Proc));
 		SET_CHIPSET(IC_LYNXPOINT);
 		break;
+	case DID_INTEL_HSW_EP_HOST_BRIDGE:
+		HSW_EP_CAP(RO(Shm), RO(Proc), RO(Core));
+		HSW_EP_IMC(RO(Shm), RO(Proc));
+		SET_CHIPSET(IC_WELLSBURG);
+		break;
 	case DID_INTEL_BROADWELL_IMC_HA0:	/* Broadwell/Y/U Core m */
 		IVB_CAP(RO(Shm), RO(Proc), RO(Core));
 		HSW_IMC(RO(Shm), RO(Proc));