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Merge pull request #7 from Banyc/fix/typo
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fix typos
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@d0iasm
d0iasm authored Aug 11, 2022
2 parents 3516146 + 33d2210 commit 58991b0
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Showing 7 changed files with 21 additions and 21 deletions.
6 changes: 3 additions & 3 deletions module/src/trap.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -159,7 +159,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -171,7 +171,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
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6 changes: 3 additions & 3 deletions step05/src/trap.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -121,7 +121,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -133,7 +133,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
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6 changes: 3 additions & 3 deletions step06/src/trap.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -121,7 +121,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -133,7 +133,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
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6 changes: 3 additions & 3 deletions step07/src/trap.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -121,7 +121,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -133,7 +133,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
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6 changes: 3 additions & 3 deletions step08/src/trap.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -159,7 +159,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -171,7 +171,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
Expand Down
6 changes: 3 additions & 3 deletions step09/src/trap.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -159,7 +159,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -171,7 +171,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
Expand Down
6 changes: 3 additions & 3 deletions step10/src/trap.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ pub trait Trap {
// instruction as described below. For other exceptions, stval is set to zero."
cpu.store_csr(STVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// Set a previous interrupt-enable bit for supervisor mode (SPIE, 5) to the value
// of a global interrupt-enable bit for supervisor mode (SIE, 1).
cpu.store_csr(
SSTATUS,
Expand Down Expand Up @@ -159,7 +159,7 @@ pub trait Trap {
// instruction as described below. For other traps, mtval is set to zero."
cpu.store_csr(MTVAL, 0);

// Set a privious interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// Set a previous interrupt-enable bit for supervisor mode (MPIE, 7) to the value
// of a global interrupt-enable bit for supervisor mode (MIE, 3).
cpu.store_csr(
MSTATUS,
Expand All @@ -171,7 +171,7 @@ pub trait Trap {
);
// Set a global interrupt-enable bit for supervisor mode (MIE, 3) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(1 << 3));
// Set a privious privilege mode for supervisor mode (MPP, 11..13) to 0.
// Set a previous privilege mode for supervisor mode (MPP, 11..13) to 0.
cpu.store_csr(MSTATUS, cpu.load_csr(MSTATUS) & !(0b11 << 11));
}
}
Expand Down

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