RTL design complete. Testbench passed.

Author: diadatp

README.md

@@ -1,2 +1,30 @@
 # mips_cpu
-A implementation of a 32-bit single cycle MIPS processor in Verilog.
+
+A implementation of a 32-bit single cycle MIPS processor in Verilog. This version of the MIPS single-cycle processor can execute the following instructions: add, sub, and, or, slt, lw, sw, beq, addi, and j.
+
+To tun the test bench:
+
+$ iverilog *.v
+$ ./a.out; gtkwave dump.vcd test.gtkw
+
+Each of the memories is a 64-word × 32-bit array. The instruction memory contains some initial values representing a test program.
+
+## Test MIPS instructions.
+
+main:	addi $2, $0, 5		# 20020005
+	addi $7, $0, 3		# 20070003
+	addi $3, $0, 0xc	# 2003000c
+	or $4, $7, $2		# 00e22025
+	and $5, $3, $4		# 00642824
+	add $5, $5, $4		# 00a42820
+	beq $5, $7, end		# 10a70008
+	slt $6, $3, $4		# 0064302a
+	beq $6, $0, around	# 10c00001
+	addi $5, $0, 10		# 2005000a
+around:	slt $6, $7, $2		# 00e2302a
+	add $7, $6, $5		# 00c53820
+	sub $7, $7, $2		# 00e23822
+	j end			# 0800000f
+	lw $7, 0($0)		# 8c070000
+end:	sw $7, 71($2)		# ac470047
+

alu.v

@@ -0,0 +1,31 @@
+module alu (
+    input  [31:0] a_in, b_in,
+    input  [ 2:0] f_in ,
+    output        zero,
+    output        c_out,
+    output [31:0] y_out
+);
+
+    wire [31:0] not_b_in;
+    assign not_b_in = ~ b_in;
+
+    wire [31:0] b_mux_not_b;
+    assign b_mux_not_b = (1'b0 == f_in[2]) ? b_in : not_b_in;
+
+    wire [31:0] fx00;
+    assign fx00 = a_in & b_mux_not_b;
+
+    wire [31:0] fx01;
+    assign fx01 = a_in | b_mux_not_b;
+
+    wire [31:0] fx10;
+    assign {c_out, fx10} = a_in + b_mux_not_b + f_in[2];
+
+    wire [31:0] fx11;
+    assign fx11 = {{31{1'b0}}, ((a_in[31] == not_b_in[31]) && (fx10[31] != a_in[31])) ? ~(fx10[31]) : fx10[31]};
+
+    assign zero = ~| y_out;
+
+    assign y_out = 2'b00 == f_in[1:0] ? fx00 : (2'b01 == f_in[1:0] ? fx01 : (2'b10 == f_in[1:0] ? fx10 : fx11 ));
+
+endmodule

aludec.v

@@ -0,0 +1,22 @@
+module aludec (
+	input  [31:0] instr     ,
+	output [ 2:0] alucontrol
+);
+
+	reg [2:0] alucontrol;
+
+	always @(instr) begin
+		casex ({instr[31:26], instr[5:0]})
+			12'b000100xxxxxx : alucontrol = 3'b110;
+			12'b001010xxxxxx : alucontrol = 3'b111;
+			12'b001000xxxxxx : alucontrol = 3'b010;
+			12'bxxxxxx100000 : alucontrol = 3'b010;
+			12'bxxxxxx100010 : alucontrol = 3'b110;
+			12'bxxxxxx100100 : alucontrol = 3'b000;
+			12'bxxxxxx100101 : alucontrol = 3'b001;
+			12'bxxxxxx101010 : alucontrol = 3'b111;
+			default          : alucontrol = 3'b010;
+		endcase
+	end
+
+endmodule

controller.v

@@ -0,0 +1,31 @@
+module controller (
+	input  [31:0] instr     ,
+	// other side
+	output        branch    ,
+	output        jump      ,
+	output        mem_to_reg,
+	output        mem_write ,
+	output        reg_dst   ,
+	output        reg_write ,
+	// alu side
+	output [ 2:0] alucontrol,
+	output        alu_src
+);
+
+	maindec maindec_inst (
+		.instr     (instr     ),
+		.branch    (branch    ),
+		.jump      (jump      ),
+		.mem_to_reg(mem_to_reg),
+		.mem_write (mem_write ),
+		.reg_dst   (reg_dst   ),
+		.reg_write (reg_write ),
+		.alu_src   (alu_src   )
+	);
+
+	aludec aludec_inst (
+		.instr     (instr     ),
+		.alucontrol(alucontrol)
+	);
+
+endmodule

datapath.v

@@ -0,0 +1,97 @@
+module datapath (
+	input         clk       ,
+	input         rst       ,
+	input  [ 2:0] alucontrol,
+	input         alu_src   ,
+	input         branch    ,
+	input         jump      ,
+	input         mem_to_reg,
+	input         mem_write ,
+	input         reg_dst   ,
+	input         reg_write ,
+	// imem side
+	input  [31:0] instr     ,
+	output [31:0] pc        ,
+	// dmem side
+	input  [31:0] read_data ,
+	output [31:0] alu_result,
+	output [31:0] write_data
+);
+
+	wire [31:0] pc_plus_4;
+	assign pc_plus_4 = pc + 4;
+
+	wire [31:0] pc_jump;
+	assign pc_jump = {pc_plus_4[31:28], instr[25:0], 2'b00};
+
+	wire pc_src;
+	assign pc_src = branch & zero;
+
+	wire [31:0] pc_branch;
+	assign pc_branch = pc_plus_4 + {imm_ext[29:0], 2'b00};
+
+	wire [31:0] pc_next;
+	assign pc_next = jump ? pc_jump : (pc_src ? pc_branch : pc_plus_4);
+
+	reg [31:0] pc;
+	always @(posedge clk) begin : proc_pc
+		if(~rst) begin
+			pc = pc_next;
+		end else begin
+			pc = 32'h00000000;
+		end
+	end
+
+	wire [5:0] rt;
+	assign rt = instr[20:16];
+
+	wire [5:0] rd;
+	assign rd = instr[15:11];
+
+	wire [4:0] write_reg;
+	assign write_reg = reg_dst ? rd : rt;
+
+	wire [31:0] result;
+	assign result = mem_to_reg ? read_data : alu_result ;
+
+	wire [31:0] reg_data1;
+	wire [31:0] reg_data2;
+
+	regfile regfile_inst (
+		.clk  (clk         ),
+		.rw   (reg_write   ),
+		.addr1(instr[25:21]),
+		.addr2(instr[20:16]),
+		.addr3(write_reg   ),
+		.wdata(result      ),
+		.data1(reg_data1   ),
+		.data2(reg_data2   )
+	);
+
+	wire [31:0] src_a;
+	wire [31:0] src_b;
+	wire c_out;
+
+	assign src_a = reg_data1;
+	assign src_b = alu_src ? imm_ext : reg_data2;
+
+	alu alu_inst (
+		.a_in (src_a     ),
+		.b_in (src_b     ),
+		.f_in (alucontrol),
+		.zero (zero      ),
+		.c_out(c_out     ),
+		.y_out(alu_out   )
+	);
+	wire [31:0] alu_out;
+	assign alu_result = alu_out;
+
+	wire [31:0] imm_ext;
+	sign_extend sign_extend_inst (
+		.idata(instr[15:0]),
+		.odata(imm_ext    )
+	);
+
+	assign write_data = reg_data2;
+
+endmodule

dmem.v

@@ -0,0 +1,23 @@
+module dmem (
+	input         clk  ,
+	input         we   ,
+	input  [31:0] addr ,
+	input  [31:0] wdata,
+	output [31:0] rdata
+);
+
+	reg [31:0] rdata;
+
+	reg [31:0] memdata[63:0];
+
+	always @(memdata[addr]) begin
+		rdata = memdata[addr];
+	end
+
+	always @(posedge clk) begin
+		if(1'b1 == we) begin
+			memdata[addr] = wdata;
+		end
+	end
+
+endmodule

imem.v

@@ -0,0 +1,79 @@
+module imem (
+	input  [ 5:0] addr,
+	output [31:0] data
+);
+
+	reg [31:0] data;
+
+	// echo -e {00..63}": data = 32'h00000000;\n"
+	// xx : data = {6'dx,5'dx,5'dx,5'dx,5'dx,6'dx};
+	always @(addr) begin
+		case(addr)
+			00 : data = 32'h20020005;
+			01 : data = 32'h20070003;
+			02 : data = 32'h2003000c;
+			03 : data = 32'h00e22025;
+			04 : data = 32'h00642824;
+			05 : data = 32'h00a42820;
+			06 : data = 32'h10a70008;
+			07 : data = 32'h0064302a;
+			08 : data = 32'h10c00001;
+			09 : data = 32'h2005000a;
+			10 : data = 32'h00e2302a;
+			11 : data = 32'h00c53820;
+			12 : data = 32'h00e23822;
+			13 : data = 32'h0800000f;
+			14 : data = 32'h8c070000;
+			15 : data = 32'hac470047;
+			16 : data = 32'h00000000;
+			17 : data = 32'h00000000;
+			18 : data = 32'h00000000;
+			19 : data = 32'h00000000;
+			20 : data = 32'h00000000;
+			21 : data = 32'h00000000;
+			22 : data = 32'h00000000;
+			23 : data = 32'h00000000;
+			24 : data = 32'h00000000;
+			25 : data = 32'h00000000;
+			26 : data = 32'h00000000;
+			27 : data = 32'h00000000;
+			28 : data = 32'h00000000;
+			29 : data = 32'h00000000;
+			30 : data = 32'h00000000;
+			31 : data = 32'h00000000;
+			32 : data = 32'h00000000;
+			33 : data = 32'h00000000;
+			34 : data = 32'h00000000;
+			35 : data = 32'h00000000;
+			36 : data = 32'h00000000;
+			37 : data = 32'h00000000;
+			38 : data = 32'h00000000;
+			39 : data = 32'h00000000;
+			40 : data = 32'h00000000;
+			41 : data = 32'h00000000;
+			42 : data = 32'h00000000;
+			43 : data = 32'h00000000;
+			44 : data = 32'h00000000;
+			45 : data = 32'h00000000;
+			46 : data = 32'h00000000;
+			47 : data = 32'h00000000;
+			48 : data = 32'h00000000;
+			49 : data = 32'h00000000;
+			50 : data = 32'h00000000;
+			51 : data = 32'h00000000;
+			52 : data = 32'h00000000;
+			53 : data = 32'h00000000;
+			54 : data = 32'h00000000;
+			55 : data = 32'h00000000;
+			56 : data = 32'h00000000;
+			57 : data = 32'h00000000;
+			58 : data = 32'h00000000;
+			59 : data = 32'h00000000;
+			60 : data = 32'h00000000;
+			61 : data = 32'h00000000;
+			62 : data = 32'h00000000;
+			63 : data = 32'h00000000;
+		endcase
+	end
+
+endmodule

maindec.v

@@ -0,0 +1,40 @@
+module maindec (
+	input  [31:0] instr     ,
+	//
+	output        branch    ,
+	output        jump      ,
+	output        mem_to_reg,
+	output        mem_write ,
+	output        reg_dst   ,
+	output        reg_write ,
+	output        alu_src
+);
+
+	wire [5:0] opcode;
+	assign opcode = instr[31:26];
+
+	wire [5:0] func;
+	assign func = instr[5:0];
+
+	wire is_add = ((opcode == 6'h00) & (func == 6'h20));
+	wire is_sub = ((opcode == 6'h00) & (func == 6'h22));
+	wire is_and = ((opcode == 6'h00) & (func == 6'h24));
+	wire is_or  = ((opcode == 6'h00) & (func == 6'h25));
+	wire is_slt = ((opcode == 6'h00) & (func == 6'h2A));
+
+	wire is_lw = (opcode == 6'h23);
+	wire is_sw = (opcode == 6'h2B);
+
+	wire is_beq  = (opcode == 6'h04);
+	wire is_addi = (opcode == 6'h08);
+	wire is_j    = (opcode == 6'h02);
+
+	assign branch     = is_beq;
+	assign jump       = is_j;
+	assign mem_to_reg = is_lw;
+	assign mem_write  = is_sw;
+	assign reg_dst    = is_add | is_sub | is_and | is_or | is_slt;
+	assign reg_write  = is_add | is_sub | is_and | is_or | is_slt | is_addi | is_lw;
+	assign alu_src    = is_addi | is_lw | is_sw;
+
+endmodule