diff --git a/regression/verilog/expressions/cast_from_real2.desc b/regression/verilog/expressions/cast_from_real2.desc
new file mode 100644
index 00000000..c1552ed9
--- /dev/null
+++ b/regression/verilog/expressions/cast_from_real2.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+cast_from_real2.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The implicit cast is currently not allowed.
diff --git a/regression/verilog/expressions/cast_from_real2.sv b/regression/verilog/expressions/cast_from_real2.sv
new file mode 100644
index 00000000..4b619e94
--- /dev/null
+++ b/regression/verilog/expressions/cast_from_real2.sv
@@ -0,0 +1,17 @@
+module main;
+
+  int a, b, c, d;
+
+  // implicit casting as part of an assignment
+  initial begin
+    a = 0.0;
+    assert(a == 0);
+    b = 1.0;
+    assert(b == 1);
+    c = 0.5;
+    assert(c == 1);
+    d = -0.5;
+    assert(d == -1);
+  end
+
+endmodule