From b4ce1eb3c56f9a36dbdb7daafa181e40c0dd6b30 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Thu, 21 Nov 2024 14:15:07 -0800 Subject: [PATCH] SystemVerilog: type parameter ports This implements grammar for SystemVerilog type parameter ports. --- regression/verilog/modules/parameter_ports4.desc | 3 +-- src/verilog/parser.y | 10 ++++++++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/regression/verilog/modules/parameter_ports4.desc b/regression/verilog/modules/parameter_ports4.desc index 6163170fc..818f58558 100644 --- a/regression/verilog/modules/parameter_ports4.desc +++ b/regression/verilog/modules/parameter_ports4.desc @@ -1,8 +1,7 @@ -KNOWNBUG +CORE parameter_ports4.sv --bound 0 ^EXIT=0$ ^SIGNAL=0$ -- -- -The type parameter port needs to be parsed as a type. diff --git a/src/verilog/parser.y b/src/verilog/parser.y index 5fbc846fd..c27eb31f5 100644 --- a/src/verilog/parser.y +++ b/src/verilog/parser.y @@ -1763,11 +1763,15 @@ list_of_variable_identifiers: parameter_port_declaration: TOK_PARAMETER data_type_or_implicit param_assignment { $$ = $3; } + | TOK_PARAMETER TOK_TYPE data_type_or_implicit param_assignment + { $$ = $4; } | TOK_LOCALPARAM data_type_or_implicit param_assignment { $$ = $3; } | data_type param_assignment { $$ = $2; } | param_assignment + | TOK_TYPE param_assignment + { $$ = $2; } ; list_of_defparam_assignments: @@ -1789,13 +1793,15 @@ list_of_param_assignments: { $$=$1; mto($$, $3); } ; -param_assignment: param_identifier '=' constant_param_expression +param_assignment: + param_identifier '=' constant_param_expression { init($$, ID_parameter); auto base_name = stack_expr($1).id(); stack_expr($$).set(ID_identifier, base_name); stack_expr($$).set(ID_base_name, base_name); addswap($$, ID_value, $3); } - ; + | type_assignment + ; list_of_type_assignments: type_assignment