We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
spice ignores case, verilog (by default?) doesn't.
netgen's LVS can go either way - ignoring case is spice file is read first, considering case if verilog is read first.
This can cause problems (failure to match) when the layout has cells with conflicting case, eg. Buffer and BUFFER.
Buffer
BUFFER
Suggested solution is to flag cell names and text/nets that have mixed case in the layout, spice and verilog files.
The text was updated successfully, but these errors were encountered:
No branches or pull requests
spice ignores case, verilog (by default?) doesn't.
netgen's LVS can go either way - ignoring case is spice file is read first, considering case if verilog is read first.
This can cause problems (failure to match) when the layout has cells with conflicting case, eg.
BufferandBUFFER.Suggested solution is to flag cell names and text/nets that have mixed case in the layout, spice and verilog files.
The text was updated successfully, but these errors were encountered: