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Pull requests: enjoy-digital/litex

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Pull requests list

soc/interconnect/axi: fix up-converter lane handling
#2466 opened May 24, 2026 by enjoy-digital Owner Loading…
build: add reproducible build bundles and remote replay.
#2465 opened May 21, 2026 by enjoy-digital Owner Loading…
PoC: model-based AXI-Lite tests + converter regression
#2402 opened Jan 21, 2026 by cklarhorst Contributor Loading…
integration/builder: Add bios selftest option
#2393 opened Jan 9, 2026 by cklarhorst Contributor Loading…
Fixed ROM size and endianness
#2338 opened Sep 27, 2025 by franos-cm Loading…
build: efinix: efinity: hide excluded ios
#2290 opened Jul 23, 2025 by maass-hamburg Contributor Draft
Add RISC-V CLIC and CLINT interrupt controller support
#2260 opened Jun 15, 2025 by disdi Loading…
Fix for wire/reg issue
#2255 opened Jun 9, 2025 by Ka-zam Contributor Loading…
soc/cores/cpu/zynq7000/core.py: added support for openXC7/yosys/nextPNR
#2243 opened May 13, 2025 by trabucayre Collaborator Loading…
Add disting to pypi to release steps
#2219 opened Mar 28, 2025 by timkpaine Contributor Draft
soc/interconnect/wishbone: Add Wishbone CDC
#2158 opened Jan 13, 2025 by david-sawatzke Contributor Loading…
Add (optional) clock parameter when instantiating xgmii module
#2154 opened Jan 7, 2025 by david-sawatzke Contributor Loading…
tests: Improve GitHub CI action
#2144 opened Dec 18, 2024 by FlyGoat Contributor Loading…
bios: add flash_transfer_cmd
#2106 opened Oct 26, 2024 by cklarhorst Contributor Loading…
BIOS: Add BOOTP support
#2070 opened Sep 12, 2024 by m-byte Contributor Loading…
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