fix(esp_hw_support): fix branch predictor access flash after cache disabled

Author: esp-wzh

components/esp_hw_support/sleep_modes.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -56,7 +56,6 @@
 #include "soc/rtc.h"
 #include "regi2c_ctrl.h"    //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp
 
-#include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/wdt_hal.h"
@@ -70,6 +69,7 @@
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
+#include "esp_private/cache_utils.h"
 #include "esp_private/brownout.h"
 #include "esp_private/sleep_console.h"
 #include "esp_private/sleep_cpu.h"
@@ -494,7 +494,7 @@ static int s_cache_suspend_cnt = 0;
 static void IRAM_ATTR suspend_cache(void) {
     s_cache_suspend_cnt++;
     if (s_cache_suspend_cnt == 1) {
-        cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+        spi_flash_disable_cache(esp_cpu_get_core_id(), NULL);
     }
 }
 
@@ -503,7 +503,7 @@ static void IRAM_ATTR resume_cache(void) {
     s_cache_suspend_cnt--;
     assert(s_cache_suspend_cnt >= 0 && DRAM_STR("cache resume doesn't match suspend ops"));
     if (s_cache_suspend_cnt == 0) {
-        cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+        spi_flash_restore_cache(esp_cpu_get_core_id(), 0);
     }
 }
 

components/esp_system/port/cpu_start.c

@@ -62,6 +62,7 @@
 #include "esp_memprot.h"
 #endif
 
+#include "esp_private/cache_utils.h"
 #include "esp_private/rtc_clk.h"
 #include "esp_rtc_time.h"
 #include "rom/rtc.h"
@@ -686,7 +687,6 @@ void IRAM_ATTR call_start_cpu0(void)
 #if CONFIG_ESP32S2_DATA_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
     dcache_wrap_enable = 1;
 #endif
-    extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
     esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
 #endif
 
@@ -698,7 +698,6 @@ void IRAM_ATTR call_start_cpu0(void)
 #if CONFIG_IDF_TARGET_ESP32C2
 // TODO : IDF-5020
 #if CONFIG_ESP32C2_INSTRUCTION_CACHE_WRAP
-    extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable);
     esp_enable_cache_wrap(1);
 #endif
 #endif

components/spi_flash/cache_utils.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,21 +33,14 @@
 #include "esp_memory_utils.h"
 #include "esp_intr_alloc.h"
 #include "spi_flash_override.h"
+#include "esp_private/cache_utils.h"
 #include "esp_private/spi_flash_os.h"
 #include "esp_private/freertos_idf_additions_priv.h"
 #include "esp_log.h"
 #include "esp_cpu.h"
 
 static __attribute__((unused)) const char *TAG = "cache";
 
-
-/**
- * These two shouldn't be declared as static otherwise if `CONFIG_SPI_FLASH_ROM_IMPL` is enabled,
- * they won't get replaced by the rom version
- */
-void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
-void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
-
 // Used only on ROM impl. in idf, this param unused, cache status hold by hal
 static uint32_t s_flash_op_cache_state[2];
 

components/spi_flash/include/esp_private/cache_utils.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -64,7 +64,22 @@ bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length);
 void esp_config_instruction_cache_mode(void);
 //config data cache size and cache block size by menuconfig
 void esp_config_data_cache_mode(void);
-//enable cache wrap mode for instruction cache and data cache
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
+/**
+ * @brief   enable cache wrap mode for i/d shared cache
+ * @param   icache_wrap_enable  enable cache wrap mode for i/d shared cache
+ * @return  ESP_OK on success, ESP_FAIL otherwise
+ */
+esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable);
+#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32S2
+/**
+ * @brief  enable cache wrap mode for instruction cache and data cache
+ * @param  icache_wrap_enable   enable cache wrap mode for i cache
+ * @param  dcache_wrap_enable   enable cache wrap mode for d cache
+ * @return ESP_OK on success, ESP_FAIL otherwise
+ */
 esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable);
 #endif
 
@@ -81,6 +96,22 @@ bool spi_flash_cache_enabled(void);
  */
 void spi_flash_enable_cache(uint32_t cpuid);
 
+/**
+ * @brief Suspend the Cache access to external memory, will disable branch predictor if supported.
+ *
+ * @param cpuid       the core number to enable the cache for, meaning less on shared cache.
+ * @param saved_state Cache status hold by hal (Used only on ROM impl. in idf, this param unused)
+ */
+void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
+
+/**
+ * @brief Resume the Cache access to external memory, will enable branch predictor if supported.
+ *
+ * @param cpuid       the core number to enable the cache for, meaning less on shared cache.
+ * @param saved_state Cache status hold by hal (Used only on ROM impl. in idf, this param unused)
+ */
+void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
+
 #ifdef __cplusplus
 }
 #endif