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FL0WL0WFL0WL0W
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Use configuration option instead of in components not related to FreeRTOS
1 parent ab03c2e commit c235f7b

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57 files changed

+127
-127
lines changed

‎components/app_trace/Kconfig

+4-4
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ menu "Application Level Tracing"
231231

232232
choice APPTRACE_SV_CPU
233233
prompt "CPU to trace"
234-
depends on APPTRACE_SV_DEST_UART && !FREERTOS_UNICORE
234+
depends on APPTRACE_SV_DEST_UART && !ESP_SYSTEM_SINGLE_CORE_MODE
235235
default APPTRACE_SV_DEST_CPU_0
236236
help
237237
Define the CPU to trace by SystemView.
@@ -252,16 +252,16 @@ menu "Application Level Tracing"
252252
choice APPTRACE_SV_TS_SOURCE
253253
prompt "Timer to use as timestamp source"
254254
depends on APPTRACE_SV_ENABLE
255-
default APPTRACE_SV_TS_SOURCE_CCOUNT if FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
256-
default APPTRACE_SV_TS_SOURCE_GPTIMER if !FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
255+
default APPTRACE_SV_TS_SOURCE_CCOUNT if ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
256+
default APPTRACE_SV_TS_SOURCE_GPTIMER if !ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
257257
default APPTRACE_SV_TS_SOURCE_ESP_TIMER if PM_ENABLE || IDF_TARGET_ESP32C3
258258
help
259259
SystemView needs to use a hardware timer as the source of timestamps
260260
when tracing. This option selects the timer for it.
261261

262262
config APPTRACE_SV_TS_SOURCE_CCOUNT
263263
bool "CPU cycle counter (CCOUNT)"
264-
depends on FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
264+
depends on ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
265265

266266
config APPTRACE_SV_TS_SOURCE_GPTIMER
267267
bool "General Purpose Timer (Timer Group)"

‎components/app_trace/port/xtensa/port.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ static inline void esp_apptrace_trax_memory_enable(void)
298298
#if CONFIG_IDF_TARGET_ESP32
299299
/* Enable trace memory on PRO CPU */
300300
DPORT_WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M);
301-
#if CONFIG_FREERTOS_UNICORE == 0
301+
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE == 0
302302
/* Enable trace memory on APP CPU */
303303
DPORT_WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M);
304304
#endif

‎components/app_trace/sys_view/esp/SEGGER_RTT_esp.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ static uint8_t s_down_buf[SYSVIEW_DOWN_BUF_SIZE];
3535
#if CONFIG_APPTRACE_SV_DEST_UART
3636

3737
#define ESP_APPTRACE_DEST_SYSVIEW ESP_APPTRACE_DEST_UART
38-
#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_FREERTOS_UNICORE
38+
#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
3939
#define APPTRACE_SV_DEST_CPU 0
4040
#else
4141
#define APPTRACE_SV_DEST_CPU 1

‎components/bootloader_support/include/bootloader_memory_utils.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) {
3939
*/
4040
__attribute__((always_inline))
4141
inline static bool esp_ptr_in_iram(const void *p) {
42-
#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
42+
#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
4343
return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
4444
#else
4545
return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);

‎components/bootloader_support/src/bootloader_init.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ void bootloader_print_banner(void)
103103
#endif
104104
}
105105

106-
#if CONFIG_FREERTOS_UNICORE
106+
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
107107
#if (SOC_CPU_CORES_NUM > 1)
108108
ESP_EARLY_LOGW(TAG, "Unicore bootloader");
109109
#endif

‎components/bootloader_support/src/bootloader_utility.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -884,7 +884,7 @@ static void set_cache_and_start_app(
884884
bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
885885
cache_ll_l1_enable_bus(0, bus_mask);
886886

887-
#if !CONFIG_FREERTOS_UNICORE
887+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
888888
bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
889889
cache_ll_l1_enable_bus(1, bus_mask);
890890
bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);

‎components/bootloader_support/src/esp32/bootloader_esp32.c

+6-6
Original file line numberDiff line numberDiff line change
@@ -44,15 +44,15 @@ static void bootloader_reset_mmu(void)
4444
{
4545
/* completely reset MMU in case serial bootloader was running */
4646
Cache_Read_Disable(0);
47-
#if !CONFIG_FREERTOS_UNICORE
47+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
4848
Cache_Read_Disable(1);
4949
#endif
5050
Cache_Flush(0);
51-
#if !CONFIG_FREERTOS_UNICORE
51+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
5252
Cache_Flush(1);
5353
#endif
5454
mmu_init(0);
55-
#if !CONFIG_FREERTOS_UNICORE
55+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
5656
/* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
5757
necessary to work around a hardware bug. */
5858
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
@@ -63,7 +63,7 @@ static void bootloader_reset_mmu(void)
6363
/* normal ROM boot exits with DROM0 cache unmasked,
6464
but serial bootloader exits with it masked. */
6565
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
66-
#if !CONFIG_FREERTOS_UNICORE
66+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
6767
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
6868
#endif
6969
}
@@ -104,7 +104,7 @@ static void wdt_reset_info_dump(int cpu)
104104
lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
105105
lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
106106
} else {
107-
#if !CONFIG_FREERTOS_UNICORE
107+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
108108
stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
109109
pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
110110
inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
@@ -154,7 +154,7 @@ static void bootloader_check_wdt_reset(void)
154154
if (wdt_rst) {
155155
// if reset by WDT dump info from trace port
156156
wdt_reset_info_dump(0);
157-
#if !CONFIG_FREERTOS_UNICORE
157+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
158158
wdt_reset_info_dump(1);
159159
#endif
160160
}

‎components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ static void bootloader_check_wdt_reset(void)
7272
if (wdt_rst) {
7373
// if reset by WDT dump info from trace port
7474
wdt_reset_info_dump(0);
75-
#if !CONFIG_FREERTOS_UNICORE
75+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
7676
wdt_reset_info_dump(1);
7777
#endif
7878
}

‎components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ static void wdt_reset_info_dump(int cpu)
7070
lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
7171
lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
7272
} else {
73-
#if !CONFIG_FREERTOS_UNICORE
73+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
7474
inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
7575
dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
7676
data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
@@ -115,7 +115,7 @@ static void bootloader_check_wdt_reset(void)
115115
if (wdt_rst) {
116116
// if reset by WDT dump info from trace port
117117
wdt_reset_info_dump(0);
118-
#if !CONFIG_FREERTOS_UNICORE
118+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
119119
wdt_reset_info_dump(1);
120120
#endif
121121
}

‎components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -96,13 +96,13 @@ void esp_gdbstub_init_dports(void)
9696

9797
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
9898

99-
#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
99+
#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
100100
static bool stall_started = false;
101101
#endif
102102

103103
void esp_gdbstub_stall_other_cpus_start(void)
104104
{
105-
#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
105+
#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
106106
if (stall_started == false) {
107107
esp_ipc_isr_stall_other_cpu();
108108
stall_started = true;
@@ -112,7 +112,7 @@ void esp_gdbstub_stall_other_cpus_start(void)
112112

113113
void esp_gdbstub_stall_other_cpus_end(void)
114114
{
115-
#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
115+
#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
116116
if (stall_started == true) {
117117
esp_ipc_isr_release_other_cpu();
118118
stall_started = false;
@@ -142,7 +142,7 @@ void esp_gdbstub_do_step(esp_gdbstub_frame_t *frame)
142142

143143
void esp_gdbstub_trigger_cpu(void)
144144
{
145-
#if !CONFIG_FREERTOS_UNICORE
145+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
146146
if (0 == esp_cpu_get_core_id()) {
147147
esp_crosscore_int_send_gdb_call(1);
148148
} else {

‎components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ void esp_gdbstub_init_dports(void)
132132
{
133133
}
134134

135-
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
135+
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
136136
static bool stall_started = false;
137137
#endif
138138

@@ -141,7 +141,7 @@ static bool stall_started = false;
141141
* */
142142
void esp_gdbstub_stall_other_cpus_start(void)
143143
{
144-
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
144+
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
145145
if (stall_started == false) {
146146
esp_ipc_isr_stall_other_cpu();
147147
stall_started = true;
@@ -154,7 +154,7 @@ void esp_gdbstub_stall_other_cpus_start(void)
154154
* */
155155
void esp_gdbstub_stall_other_cpus_end(void)
156156
{
157-
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
157+
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
158158
if (stall_started == true) {
159159
esp_ipc_isr_release_other_cpu();
160160
stall_started = false;
@@ -193,7 +193,7 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame)
193193
* */
194194
void esp_gdbstub_trigger_cpu(void)
195195
{
196-
#if !CONFIG_FREERTOS_UNICORE
196+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
197197
if (0 == esp_cpu_get_core_id()) {
198198
esp_crosscore_int_send_gdb_call(1);
199199
} else {

‎components/esp_hw_support/include/dport_access.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
extern "C" {
1414
#endif
1515

16-
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
16+
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND
1717
#define DPORT_STALL_OTHER_CPU_START()
1818
#define DPORT_STALL_OTHER_CPU_END()
1919
#else

‎components/esp_hw_support/include/esp_memory_utils.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) {
3939
*/
4040
__attribute__((always_inline))
4141
inline static bool esp_ptr_in_iram(const void *p) {
42-
#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
42+
#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
4343
return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
4444
#else
4545
return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
@@ -230,7 +230,7 @@ inline static bool esp_ptr_executable(const void *p)
230230
return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
231231
|| (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
232232
|| (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
233-
#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
233+
#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE)
234234
|| (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
235235
#endif
236236
#if SOC_RTC_FAST_MEM_SUPPORTED

‎components/esp_hw_support/include/spinlock.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ typedef struct {
5151
static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock)
5252
{
5353
assert(lock);
54-
#if !CONFIG_FREERTOS_UNICORE
54+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
5555
lock->owner = SPINLOCK_FREE;
5656
lock->count = 0;
5757
#endif
@@ -73,7 +73,7 @@ static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t
7373
*/
7474
static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *lock, int32_t timeout)
7575
{
76-
#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
76+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
7777
uint32_t irq_status;
7878
uint32_t core_owner_id, other_core_owner_id;
7979
bool lock_set;
@@ -151,7 +151,7 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l
151151
#endif
152152
return lock_set;
153153

154-
#else // !CONFIG_FREERTOS_UNICORE
154+
#else // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
155155
return true;
156156
#endif
157157
}
@@ -171,7 +171,7 @@ static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *l
171171
*/
172172
static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *lock)
173173
{
174-
#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
174+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
175175
uint32_t irq_status;
176176
uint32_t core_owner_id;
177177

@@ -198,7 +198,7 @@ static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *l
198198
#else
199199
rv_utils_restore_intlevel(irq_status);
200200
#endif //#if __XTENSA__
201-
#endif //#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
201+
#endif //#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
202202
}
203203

204204
#ifdef __cplusplus

‎components/esp_mm/cache_esp32.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ void cache_sync(void)
2727
}
2828

2929
s_cache_drv.cache_flush(0);
30-
#if !CONFIG_FREERTOS_UNICORE
30+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
3131
s_cache_drv.cache_flush(1);
32-
#endif // !CONFIG_FREERTOS_UNICORE
32+
#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
3333
}

‎components/esp_mm/esp_mmu_map.c

+5-5
Original file line numberDiff line numberDiff line change
@@ -402,9 +402,9 @@ FORCE_INLINE_ATTR uint32_t s_mapping_operation(mmu_target_t target, uint32_t vad
402402

403403
mmu_hal_map_region(0, target, vaddr_start, paddr_start, size, &actual_mapped_len);
404404
#if (SOC_MMU_PERIPH_NUM == 2)
405-
#if !CONFIG_FREERTOS_UNICORE
405+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
406406
mmu_hal_map_region(1, target, vaddr_start, paddr_start, size, &actual_mapped_len);
407-
#endif // #if !CONFIG_FREERTOS_UNICORE
407+
#endif // #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
408408
#endif // #if (SOC_MMU_PERIPH_NUM == 2)
409409

410410
return actual_mapped_len;
@@ -424,7 +424,7 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v
424424

425425
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);
426426
cache_ll_l1_enable_bus(0, bus_mask);
427-
#if !CONFIG_FREERTOS_UNICORE
427+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
428428
bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);
429429
cache_ll_l1_enable_bus(1, bus_mask);
430430
#endif
@@ -602,9 +602,9 @@ FORCE_INLINE_ATTR void s_unmapping_operation(uint32_t vaddr_start, uint32_t size
602602
{
603603
mmu_hal_unmap_region(0, vaddr_start, size);
604604
#if (SOC_MMU_PERIPH_NUM == 2)
605-
#if !CONFIG_FREERTOS_UNICORE
605+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
606606
mmu_hal_unmap_region(1, vaddr_start, size);
607-
#endif // #if !CONFIG_FREERTOS_UNICORE
607+
#endif // #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
608608
#endif // #if (SOC_MMU_PERIPH_NUM == 2)
609609
}
610610
#endif

‎components/esp_psram/esp32/esp_psram_extram_cache.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
#include "esp_psram.h"
1010
#include "esp_private/esp_psram_extram.h"
1111

12-
#if CONFIG_FREERTOS_UNICORE
12+
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
1313
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
1414
#else
1515
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
@@ -38,7 +38,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
3838
cache_was_disabled |= (1 << 0);
3939
DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
4040
}
41-
#ifndef CONFIG_FREERTOS_UNICORE
41+
#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
4242
if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) {
4343
cache_was_disabled |= (1 << 1);
4444
DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
@@ -70,7 +70,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
7070
while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
7171
DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
7272
}
73-
#ifndef CONFIG_FREERTOS_UNICORE
73+
#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
7474
if (cache_was_disabled & (1 << 1)) {
7575
while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
7676
DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);

‎components/esp_psram/esp32/esp_psram_impl_quad.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ typedef enum {
201201
PSRAM_VADDR_MODE_EVENODD, ///< App and pro CPU share external RAM caches: pro CPU does even 32yte ranges, app does odd ones.
202202
} psram_vaddr_mode_t;
203203

204-
#if CONFIG_FREERTOS_UNICORE
204+
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
205205
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
206206
#else
207207
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH

‎components/esp_psram/esp32s2/esp_psram_impl_quad.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -531,7 +531,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
531531
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
532532
SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
533533

534-
#if !CONFIG_FREERTOS_UNICORE
534+
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
535535
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT);
536536
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT);
537537
if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {

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