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suda-morrissuda-morris
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Merge branch 'change/update_gdma_register_esp32c61' into 'master'
change(dma): update gdma register of esp32c61 See merge request espressif/esp-idf!36028
2 parents 5700288 + 876a747 commit cc9fb5b

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-493
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+677
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‎components/esp_hw_support/test_apps/dma/main/test_gdma.c

+35-15
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -76,14 +76,24 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
7676
channel_config.sibling_chan = NULL;
7777
TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[0]));
7878

79-
TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
79+
gdma_trigger_t fake_ahb_trigger1 = {
80+
.periph = 1,
81+
.bus_id = SOC_GDMA_BUS_AHB,
82+
.instance_id = 0,
83+
};
84+
gdma_trigger_t fake_ahb_trigger2 = {
85+
.periph = 2,
86+
.bus_id = SOC_GDMA_BUS_AHB,
87+
.instance_id = 1,
88+
};
89+
TEST_ESP_OK(gdma_connect(tx_channels[0], fake_ahb_trigger1));
8090
// can't connect multiple channels to the same peripheral
81-
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
82-
TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
91+
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], fake_ahb_trigger1));
92+
TEST_ESP_OK(gdma_connect(tx_channels[1], fake_ahb_trigger2));
8393

84-
TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
8594
// but rx and tx can connect to the same peripheral
86-
TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
95+
TEST_ESP_OK(gdma_connect(rx_channels[0], fake_ahb_trigger1));
96+
TEST_ESP_OK(gdma_connect(rx_channels[1], fake_ahb_trigger2));
8797
for (int i = 0; i < 2; i++) {
8898
TEST_ESP_OK(gdma_disconnect(tx_channels[i]));
8999
TEST_ESP_OK(gdma_disconnect(rx_channels[i]));
@@ -135,14 +145,24 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
135145
channel_config.sibling_chan = NULL;
136146
TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[0]));
137147

138-
TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
148+
gdma_trigger_t fake_axi_trigger1 = {
149+
.periph = 1,
150+
.bus_id = SOC_GDMA_BUS_AXI,
151+
.instance_id = 0,
152+
};
153+
gdma_trigger_t fake_axi_trigger2 = {
154+
.periph = 2,
155+
.bus_id = SOC_GDMA_BUS_AXI,
156+
.instance_id = 1,
157+
};
158+
TEST_ESP_OK(gdma_connect(tx_channels[0], fake_axi_trigger1));
139159
// can't connect multiple channels to the same peripheral
140-
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
141-
TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
160+
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], fake_axi_trigger1));
161+
TEST_ESP_OK(gdma_connect(tx_channels[1], fake_axi_trigger2));
142162

143-
TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
144163
// but rx and tx can connect to the same peripheral
145-
TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
164+
TEST_ESP_OK(gdma_connect(rx_channels[0], fake_axi_trigger1));
165+
TEST_ESP_OK(gdma_connect(rx_channels[1], fake_axi_trigger2));
146166
for (int i = 0; i < 2; i++) {
147167
TEST_ESP_OK(gdma_disconnect(tx_channels[i]));
148168
TEST_ESP_OK(gdma_disconnect(rx_channels[i]));
@@ -153,7 +173,7 @@ TEST_CASE("GDMA channel allocation", "[GDMA]")
153173
}
154174

155175
static void test_gdma_config_link_list(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan,
156-
gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, size_t sram_alignment, bool dma_link_in_ext_mem)
176+
gdma_link_list_handle_t *tx_link_list, gdma_link_list_handle_t *rx_link_list, size_t sram_alignment, bool dma_link_in_ext_mem)
157177
{
158178

159179
gdma_strategy_config_t strategy = {
@@ -366,7 +386,7 @@ static void test_gdma_m2m_mode(bool trig_retention_backup)
366386
TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]")
367387
{
368388
test_gdma_m2m_mode(false);
369-
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
389+
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION
370390
// test again with retention
371391
test_gdma_m2m_mode(true);
372392
#endif
@@ -384,7 +404,7 @@ static bool test_gdma_m2m_unalgined_rx_eof_callback(gdma_channel_handle_t dma_ch
384404
BaseType_t task_woken = pdFALSE;
385405
test_gdma_context_t *user_ctx = (test_gdma_context_t*)user_data;
386406
for (int i = 0; i < 3; i++) {
387-
if(user_ctx->align_array->aligned_buffer[i].aligned_buffer && user_ctx->need_invalidate) {
407+
if (user_ctx->align_array->aligned_buffer[i].aligned_buffer && user_ctx->need_invalidate) {
388408
TEST_ESP_OK(esp_cache_msync(user_ctx->align_array->aligned_buffer[i].aligned_buffer, ALIGN_UP(user_ctx->align_array->aligned_buffer[i].length, user_ctx->split_alignment), ESP_CACHE_MSYNC_FLAG_DIR_M2C));
389409
}
390410
}
@@ -471,7 +491,7 @@ static void test_gdma_m2m_unalgined_buffer_test(uint8_t *dst_data, uint8_t *src_
471491

472492
// validate the destination data
473493
for (int i = 0; i < data_length; i++) {
474-
TEST_ASSERT_EQUAL(i % 256 , dst_data[i + offset_len]);
494+
TEST_ASSERT_EQUAL(i % 256, dst_data[i + offset_len]);
475495
}
476496

477497
free(stash_buffer);

‎components/hal/esp32c61/include/hal/ahb_dma_ll.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ extern "C" {
2727
#define GDMA_LL_TX_EVENT_MASK (0x3F)
2828

2929
// any "dummy" peripheral ID can be used for M2M mode
30-
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31)
30+
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFE75)
3131
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
3232

3333
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)

‎components/soc/esp32c61/include/soc/gdma_channel.h

-2
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
1010
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
1111
#define SOC_GDMA_TRIG_PERIPH_SPI2 (1)
12-
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
1312
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
1413
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
1514
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
@@ -20,7 +19,6 @@
2019

2120
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
2221
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
23-
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
2422
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
2523
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
2624
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB

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