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9 | 9 | # this will generate new source files, next rebuild all the sources.
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10 | 10 | # !!!!!!!!!!! #
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11 | 11 |
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12 |
| -# This file was generated by regtools.py based on the efuses.yaml file with the version: b09fa417de505238a601eddce188b696 |
| 12 | +# This file was generated by regtools.py based on the efuses.yaml file with the version: 287a0ed4951aba84b9571a5f31000275 |
13 | 13 |
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14 | 14 | WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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15 | 15 | WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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@@ -79,8 +79,30 @@ WR_DIS.PA_TRIM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis
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79 | 79 | WR_DIS.TRIM_N_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_N_BIAS
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80 | 80 | WR_DIS.TRIM_P_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_P_BIAS
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81 | 81 | WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
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| 82 | +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS |
| 83 | +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS |
| 84 | +WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG |
| 85 | +WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS |
| 86 | +WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG |
| 87 | +WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS |
| 88 | +WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP |
82 | 89 | WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
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| 90 | +WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR |
83 | 91 | WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
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| 92 | +WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 |
| 93 | +WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 |
| 94 | +WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 |
| 95 | +WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 |
| 96 | +WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0 |
| 97 | +WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1 |
| 98 | +WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2 |
| 99 | +WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3 |
| 100 | +WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF |
| 101 | +WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF |
| 102 | +WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF |
| 103 | +WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF |
| 104 | +WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF |
| 105 | +WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF |
84 | 106 | WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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85 | 107 | WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
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86 | 108 | WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
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@@ -173,8 +195,30 @@ PKG_VERSION, EFUSE_BLK1, 90, 3, [] Packag
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173 | 195 | PA_TRIM_VERSION, EFUSE_BLK1, 93, 3, [] PADC CAL PA trim version
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174 | 196 | TRIM_N_BIAS, EFUSE_BLK1, 96, 5, [] PADC CAL N bias
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175 | 197 | TRIM_P_BIAS, EFUSE_BLK1, 101, 5, [] PADC CAL P bias
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| 198 | +ACTIVE_HP_DBIAS, EFUSE_BLK1, 106, 4, [] Active HP DBIAS of fixed voltage |
| 199 | +ACTIVE_LP_DBIAS, EFUSE_BLK1, 110, 4, [] Active LP DBIAS of fixed voltage |
| 200 | +LSLP_HP_DBG, EFUSE_BLK1, 114, 2, [] LSLP HP DBG of fixed voltage |
| 201 | +LSLP_HP_DBIAS, EFUSE_BLK1, 116, 4, [] LSLP HP DBIAS of fixed voltage |
| 202 | +DSLP_LP_DBG, EFUSE_BLK1, 120, 4, [] DSLP LP DBG of fixed voltage |
| 203 | +DSLP_LP_DBIAS, EFUSE_BLK1, 124, 5, [] DSLP LP DBIAS of fixed voltage |
| 204 | +LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 129, 5, [] DBIAS gap between LP and HP |
176 | 205 | OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
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| 206 | +TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data |
177 | 207 | OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
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| 208 | +ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 145, 10, [] Average initcode of ADC1 atten0 |
| 209 | +ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 155, 10, [] Average initcode of ADC1 atten0 |
| 210 | +ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 165, 10, [] Average initcode of ADC1 atten0 |
| 211 | +ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 175, 10, [] Average initcode of ADC1 atten0 |
| 212 | +ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] HI DOUT of ADC1 atten0 |
| 213 | +ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] HI DOUT of ADC1 atten1 |
| 214 | +ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] HI DOUT of ADC1 atten2 |
| 215 | +ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] HI DOUT of ADC1 atten3 |
| 216 | +ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] Gap between ADC1 CH0 and average initcode |
| 217 | +ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] Gap between ADC1 CH1 and average initcode |
| 218 | +ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] Gap between ADC1 CH2 and average initcode |
| 219 | +ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] Gap between ADC1 CH3 and average initcode |
| 220 | +ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 241, 4, [] Gap between ADC1 CH4 and average initcode |
| 221 | +ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 245, 4, [] Gap between ADC1 CH5 and average initcode |
178 | 222 | USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
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179 | 223 | USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
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180 | 224 | KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
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