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Revert instructions where encoding is unrecognized
1 parent 8355a95 commit f01251b

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4 files changed

+61
-0
lines changed

4 files changed

+61
-0
lines changed

‎rvgo/fast/vm.go

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -666,11 +666,15 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
666666
rdValue = shr64(and64(imm, byteToU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
667667
case 0x10: // 010000 = SRAI
668668
rdValue = sar64(and64(imm, byteToU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
669+
default:
670+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x13", imm))
669671
}
670672
case 6: // 110 = ORI
671673
rdValue = or64(rs1Value, imm)
672674
case 7: // 111 = ANDI
673675
rdValue = and64(rs1Value, imm)
676+
default:
677+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x13", funct3))
674678
}
675679
setRegister(rd, rdValue)
676680
setPC(add64(pc, byteToU64(4)))
@@ -698,7 +702,11 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
698702
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), byteToU64(31))
699703
case 0x20: // 0100000 = SRAIW
700704
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(byteToU64(31), shamt))
705+
default:
706+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x1B", imm))
701707
}
708+
default:
709+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x1B", funct3))
702710
}
703711
setRegister(rd, rdValue)
704712
setPC(add64(pc, byteToU64(4)))
@@ -745,6 +753,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
745753
default:
746754
rdValue = mod64(rs1Value, rs2Value)
747755
}
756+
default:
757+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x33", funct3))
748758
}
749759
default:
750760
switch funct3 {
@@ -754,6 +764,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
754764
rdValue = add64(rs1Value, rs2Value)
755765
case 0x20: // 0100000 = SUB
756766
rdValue = sub64(rs1Value, rs2Value)
767+
default:
768+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
757769
}
758770
case 1: // 001 = SLL
759771
rdValue = shl64(and64(rs2Value, byteToU64(0x3F)), rs1Value) // only the low 6 bits are consider in RV6VI
@@ -769,11 +781,15 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
769781
rdValue = shr64(and64(rs2Value, byteToU64(0x3F)), rs1Value) // logical: fill with zeroes
770782
case 0x20: // 0100000 = SRA
771783
rdValue = sar64(and64(rs2Value, byteToU64(0x3F)), rs1Value) // arithmetic: sign bit is extended
784+
default:
785+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
772786
}
773787
case 6: // 110 = OR
774788
rdValue = or64(rs1Value, rs2Value)
775789
case 7: // 111 = AND
776790
rdValue = and64(rs1Value, rs2Value)
791+
default:
792+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3))
777793
}
778794
}
779795
setRegister(rd, rdValue)
@@ -815,6 +831,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
815831
default:
816832
rdValue = mask32Signed64(mod64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
817833
}
834+
default:
835+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3))
818836
}
819837
default:
820838
switch funct3 {
@@ -824,6 +842,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
824842
rdValue = mask32Signed64(add64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
825843
case 0x20: // 0100000 = SUBW
826844
rdValue = mask32Signed64(sub64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
845+
default:
846+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
827847
}
828848
case 1: // 001 = SLLW
829849
rdValue = mask32Signed64(shl64(and64(rs2Value, byteToU64(0x1F)), rs1Value))
@@ -834,7 +854,11 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
834854
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), byteToU64(31))
835855
case 0x20: // 0100000 = SRAW
836856
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(byteToU64(31), shamt))
857+
default:
858+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
837859
}
860+
default:
861+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3))
838862
}
839863
}
840864
setRegister(rd, rdValue)

‎rvgo/riscv/constants.go

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ const (
5151
ErrUnexpectedRProofLoad = uint64(0xbad22220)
5252
ErrUnexpectedRProofStoreUnaligned = uint64(0xbad22221)
5353
ErrUnexpectedRProofStore = uint64(0xbad2222f)
54+
ErrIllegalInstruction = uint64(0xbadc0de)
5455
ErrBadAMOSize = uint64(0xbada70)
5556
ErrFailToReadPreimage = uint64(0xbadf00d0)
5657
ErrBadMemoryProof = uint64(0xbadf00d1)

‎rvgo/slow/vm.go

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -850,11 +850,15 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
850850
rdValue = shr64(and64(imm, byteToU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
851851
case 0x10: // 010000 = SRAI
852852
rdValue = sar64(and64(imm, byteToU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
853+
default:
854+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x13", imm.val()))
853855
}
854856
case 6: // 110 = ORI
855857
rdValue = or64(rs1Value, imm)
856858
case 7: // 111 = ANDI
857859
rdValue = and64(rs1Value, imm)
860+
default:
861+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x13", funct3.val()))
858862
}
859863
setRegister(rd, rdValue)
860864
setPC(add64(pc, byteToU64(4)))
@@ -882,7 +886,11 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
882886
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), byteToU64(31))
883887
case 0x20: // 0100000 = SRAIW
884888
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(byteToU64(31), shamt))
889+
default:
890+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x1B", imm.val()))
885891
}
892+
default:
893+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x1B", funct3.val()))
886894
}
887895
setRegister(rd, rdValue)
888896
setPC(add64(pc, byteToU64(4)))
@@ -929,6 +937,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
929937
default:
930938
rdValue = mod64(rs1Value, rs2Value)
931939
}
940+
default:
941+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x33", funct3.val()))
932942
}
933943
default:
934944
switch funct3.val() {
@@ -938,6 +948,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
938948
rdValue = add64(rs1Value, rs2Value)
939949
case 0x20: // 0100000 = SUB
940950
rdValue = sub64(rs1Value, rs2Value)
951+
default:
952+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
941953
}
942954
case 1: // 001 = SLL
943955
rdValue = shl64(and64(rs2Value, byteToU64(0x3F)), rs1Value) // only the low 6 bits are consider in RV6VI
@@ -953,11 +965,15 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
953965
rdValue = shr64(and64(rs2Value, byteToU64(0x3F)), rs1Value) // logical: fill with zeroes
954966
case 0x20: // 0100000 = SRA
955967
rdValue = sar64(and64(rs2Value, byteToU64(0x3F)), rs1Value) // arithmetic: sign bit is extended
968+
default:
969+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
956970
}
957971
case 6: // 110 = OR
958972
rdValue = or64(rs1Value, rs2Value)
959973
case 7: // 111 = AND
960974
rdValue = and64(rs1Value, rs2Value)
975+
default:
976+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3.val()))
961977
}
962978
}
963979
setRegister(rd, rdValue)
@@ -999,6 +1015,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
9991015
default:
10001016
rdValue = mask32Signed64(mod64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
10011017
}
1018+
default:
1019+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3.val()))
10021020
}
10031021
default:
10041022
switch funct3.val() {
@@ -1008,6 +1026,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
10081026
rdValue = mask32Signed64(add64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
10091027
case 0x20: // 0100000 = SUBW
10101028
rdValue = mask32Signed64(sub64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
1029+
default:
1030+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
10111031
}
10121032
case 1: // 001 = SLLW
10131033
rdValue = mask32Signed64(shl64(and64(rs2Value, byteToU64(0x1F)), rs1Value))
@@ -1018,7 +1038,11 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
10181038
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), byteToU64(31))
10191039
case 0x20: // 0100000 = SRAW
10201040
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(byteToU64(31), shamt))
1041+
default:
1042+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
10211043
}
1044+
default:
1045+
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3.val()))
10221046
}
10231047
}
10241048
setRegister(rd, rdValue)

‎rvsol/src/RISCV.sol

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1267,6 +1267,7 @@ contract RISCV is IBigStepper {
12671267
// 010000 = SRAI
12681268
rdValue := sar64(and64(imm, toU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
12691269
}
1270+
default { revertWithCode(0xbadc0de) }
12701271
}
12711272
case 6 {
12721273
// 110 = ORI
@@ -1276,6 +1277,7 @@ contract RISCV is IBigStepper {
12761277
// 111 = ANDI
12771278
rdValue := and64(rs1Value, imm)
12781279
}
1280+
default { revertWithCode(0xbadc0de) }
12791281
setRegister(rd, rdValue)
12801282
setPC(add64(_pc, toU64(4)))
12811283
}
@@ -1312,7 +1314,9 @@ contract RISCV is IBigStepper {
13121314
// 0100000 = SRAIW
13131315
rdValue := signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
13141316
}
1317+
default { revertWithCode(0xbadc0de) }
13151318
}
1319+
default { revertWithCode(0xbadc0de) }
13161320
setRegister(rd, rdValue)
13171321
setPC(add64(_pc, toU64(4)))
13181322
}
@@ -1366,6 +1370,7 @@ contract RISCV is IBigStepper {
13661370
case 0 { rdValue := rs1Value }
13671371
default { rdValue := mod64(rs1Value, rs2Value) }
13681372
}
1373+
default { revertWithCode(0xbadc0de) }
13691374
}
13701375
default {
13711376
switch funct3
@@ -1380,6 +1385,7 @@ contract RISCV is IBigStepper {
13801385
// 0100000 = SUB
13811386
rdValue := sub64(rs1Value, rs2Value)
13821387
}
1388+
default { revertWithCode(0xbadc0de) }
13831389
}
13841390
case 1 {
13851391
// 001 = SLL
@@ -1409,6 +1415,7 @@ contract RISCV is IBigStepper {
14091415
// 0100000 = SRA
14101416
rdValue := sar64(and64(rs2Value, toU64(0x3F)), rs1Value) // arithmetic: sign bit is extended
14111417
}
1418+
default { revertWithCode(0xbadc0de) }
14121419
}
14131420
case 6 {
14141421
// 110 = OR
@@ -1418,6 +1425,7 @@ contract RISCV is IBigStepper {
14181425
// 111 = AND
14191426
rdValue := and64(rs1Value, rs2Value)
14201427
}
1428+
default { revertWithCode(0xbadc0de) }
14211429
}
14221430
setRegister(rd, rdValue)
14231431
setPC(add64(_pc, toU64(4)))
@@ -1467,6 +1475,7 @@ contract RISCV is IBigStepper {
14671475
rdValue := mask32Signed64(mod64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
14681476
}
14691477
}
1478+
default { revertWithCode(0xbadc0de) }
14701479
}
14711480
default {
14721481
switch funct3
@@ -1481,6 +1490,7 @@ contract RISCV is IBigStepper {
14811490
// 0100000 = SUBW
14821491
rdValue := mask32Signed64(sub64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
14831492
}
1493+
default { revertWithCode(0xbadc0de) }
14841494
}
14851495
case 1 {
14861496
// 001 = SLLW
@@ -1498,7 +1508,9 @@ contract RISCV is IBigStepper {
14981508
// 0100000 = SRAW
14991509
rdValue := signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
15001510
}
1511+
default { revertWithCode(0xbadc0de) }
15011512
}
1513+
default { revertWithCode(0xbadc0de) }
15021514
}
15031515
setRegister(rd, rdValue)
15041516
setPC(add64(_pc, toU64(4)))

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