Error related to ip:ddr4:2.2 and ip:axi_iic:2.0 for Alveo

[tahir2018]

Ciao Mr. Eugene Tarassov
While running following script to generate design block for U280 in Vivado 2023.2:

Create instance: ddr4_0, and set properties

set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
set_property -dict [ list
CONFIG.C0_CLOCK_BOARD_INTERFACE {sysclk0}
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0}
CONFIG.RESET_BOARD_INTERFACE {resetn}
] $ddr4_0

Following error is generated:
ERROR: [IP_Flow 19-3461] Value 'resetn' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'DDR/ddr4_0'.
Valid values are - Custom, pcie_perstn

Both signal resetn and pcie_perstn are included in design, so what signal should be used here, resetn or pcie_perstn?

I proceeded with resetn, by adding it after validating design with following command,
set_property CONFIG.RESET_BOARD_INTERFACE {resetn} [get_bd_cells /ddr4_0]

But while implementing design, I encountered following errors:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 3 out of 296 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless
all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].
Problem ports: iic_main_scl_io, iic_main_sda_io, and resetn.

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 3 out of 296 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: iic_main_scl_io, iic_main_sda_io, and resetn.

Can you please comment, is it due to not using pcie_perstn? or there is some other issue here.

Also similar error was reported for CONFIG.IIC_BOARD_INTERFACE {iic_main}, only I2C available in U280 is for comm with S.C, Do we have a working I2C interface in current design?
Thank you for support.