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lines changed- .github/workflows/test-build.yml+2
- .mailmap+3-3
- Makefile+1-1
- backends/verilog/verilog_backend.cc+12-5
- frontends/ast/simplify.cc+4-1
- kernel/celledges.cc+3-3
- libs/fst/00_PATCH_strict_alignment.patch+42
- libs/fst/00_UPDATE.sh+1
- libs/fst/fastlz.cc+1-20
- passes/opt/wreduce.cc+1-1
- passes/techmap/alumacc.cc+18-8
- passes/techmap/extract_fa.cc+3-2
- passes/techmap/libparse.h+4
- tests/various/bug3879.ys+29
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