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Commit f66da39

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tevadortevador
committedApr 26, 2019
Fixed some compilation issues
Code cleanup
1 parent 018c1a5 commit f66da39

12 files changed

+79
-293
lines changed
 

‎doc/program.asm

+8-8
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ randomx_isn_20:
8080
add r8, 2
8181
test r8, 254
8282
jz randomx_isn_0
83-
xor rcx, rcx
83+
xor ecx, ecx
8484
cmp r11d, 1593588996
8585
seto cl
8686
add r14, rcx
@@ -102,7 +102,7 @@ randomx_isn_24:
102102
add r8, 64
103103
test r8, 8128
104104
jz randomx_isn_21
105-
xor rcx, rcx
105+
xor ecx, ecx
106106
cmp r8d, 149087159
107107
setno cl
108108
add r14, rcx
@@ -197,7 +197,7 @@ randomx_isn_51:
197197
add r12, 128
198198
test r12, 16256
199199
jz randomx_isn_25
200-
xor rcx, rcx
200+
xor ecx, ecx
201201
cmp r11d, -1975981803
202202
setbe cl
203203
add r10, rcx
@@ -212,7 +212,7 @@ randomx_isn_54:
212212
add r8, 64
213213
test r8, 8128
214214
jz randomx_isn_52
215-
xor rcx, rcx
215+
xor ecx, ecx
216216
cmp r9d, 1917049931
217217
setns cl
218218
add r13, rcx
@@ -290,7 +290,7 @@ randomx_isn_74:
290290
add r9, 4
291291
test r9, 508
292292
jz randomx_isn_55
293-
xor rcx, rcx
293+
xor ecx, ecx
294294
cmp r11d, -1200328848
295295
setns cl
296296
add r14, rcx
@@ -352,7 +352,7 @@ randomx_isn_89:
352352
add r8, 64
353353
test r8, 8128
354354
jz randomx_isn_75
355-
xor rcx, rcx
355+
xor ecx, ecx
356356
cmp r8d, -122257389
357357
setno cl
358358
add r10, rcx
@@ -556,7 +556,7 @@ randomx_isn_143:
556556
add r14, 4
557557
test r14, 508
558558
jz randomx_isn_110
559-
xor rcx, rcx
559+
xor ecx, ecx
560560
cmp r9d, 880467599
561561
setge cl
562562
add r13, rcx
@@ -960,7 +960,7 @@ randomx_isn_247:
960960
add r9, 4
961961
test r9, 508
962962
jz randomx_isn_223
963-
xor rcx, rcx
963+
xor ecx, ecx
964964
cmp r13d, -8545330
965965
setbe cl
966966
add r10, rcx

‎makefile

+12-9
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ AR=gcc-ar
44
PLATFORM=$(shell uname -m)
55
CXXFLAGS=-std=c++11
66
CCFLAGS=
7+
ARFLAGS=rcs
78
BINDIR=bin
89
SRCDIR=src
910
TESTDIR=src/tests
@@ -21,13 +22,17 @@ ifeq ($(PLATFORM),x86_64)
2122
CXXFLAGS += -maes
2223
endif
2324

24-
release: CXXFLAGS += -march=native -O3 -flto
25-
release: CCFLAGS += -march=native -O3 -flto
25+
release: CXXFLAGS += -O3 -flto
26+
release: CCFLAGS += -O3 -flto
2627
release: LDFLAGS += -flto
2728
release: $(BINARIES)
2829

29-
nolto: CXXFLAGS += -march=native -O3
30-
nolto: CCFLAGS += -march=native -O3
30+
native: CXXFLAGS += -march=native -O3 -flto
31+
native: CCFLAGS += -march=native -O3 -flto
32+
native: $(BINARIES)
33+
34+
nolto: CXXFLAGS += -O3
35+
nolto: CCFLAGS += -O3
3136
nolto: $(BINARIES)
3237

3338
debug: CXXFLAGS += -g
@@ -42,10 +47,8 @@ profile: $(BINDIR)/benchmark
4247

4348
test: CXXFLAGS += -O0
4449

45-
$(RXA): $(RXOBJS)
46-
$(AR) rcs $@ $(RXOBJS)
47-
$(OBJDIR)/%.o: | $(OBJDIR)
48-
$(BINDIR)/%: | $(BINDIR)
50+
$(RXA): $(RXOBJS) | $(BINDIR)
51+
$(AR) $(ARFLAGS) $@ $(RXOBJS)
4952
$(OBJDIR):
5053
mkdir $(OBJDIR)
5154
$(BINDIR):
@@ -65,7 +68,7 @@ $(OBJDIR)/code-generator.o: $(TESTDIR)/code-generator.cpp $(TESTDIR)/utility.hpp
6568
$(CXX) $(CXXFLAGS) -c $< -o $@
6669
$(BINDIR)/code-generator: $(OBJDIR)/code-generator.o $(RXA)
6770
$(CXX) $(LDFLAGS) $< $(RXA) -o $@
68-
$(OBJDIR)/aes_hash.o: $(SRCDIR)/aes_hash.cpp $(SRCDIR)/soft_aes.h $(SRCDIR)/intrin_portable.h
71+
$(OBJDIR)/aes_hash.o: $(SRCDIR)/aes_hash.cpp $(SRCDIR)/soft_aes.h $(SRCDIR)/intrin_portable.h | $(OBJDIR)
6972
$(OBJDIR)/argon2_ref.o: $(SRCDIR)/argon2_ref.c $(SRCDIR)/argon2.h $(SRCDIR)/argon2_core.h \
7073
$(SRCDIR)/blake2/blamka-round-ref.h $(SRCDIR)/blake2/blake2.h \
7174
$(SRCDIR)/blake2/blake2-impl.h $(SRCDIR)/blake2/endian.h $(SRCDIR)/blake2/blake2-impl.h \

‎src/assembly_generator_x86.cpp

+26-116
Original file line numberDiff line numberDiff line change
@@ -34,15 +34,13 @@ namespace randomx {
3434
static const char* regE[4] = { "xmm4", "xmm5", "xmm6", "xmm7" };
3535
static const char* regA[4] = { "xmm8", "xmm9", "xmm10", "xmm11" };
3636

37-
static const char* regA4 = "xmm12";
38-
static const char* dblMin = "xmm13";
39-
static const char* absMask = "xmm14";
40-
static const char* signMask = "xmm15";
41-
static const char* regMx = "rbp";
37+
static const char* tempRegx = "xmm12";
38+
static const char* mantissaMask = "xmm13";
39+
static const char* exponentMask = "xmm14";
40+
static const char* scaleMask = "xmm15";
4241
static const char* regIc = "rbx";
4342
static const char* regIc32 = "ebx";
4443
static const char* regIc8 = "bl";
45-
static const char* regDatasetAddr = "rdi";
4644
static const char* regScratchpadAddr = "rsi";
4745

4846
void AssemblyGeneratorX86::generateProgram(Program& prog) {
@@ -274,7 +272,6 @@ namespace randomx {
274272
return (int32_t)instr.getImm32() & ScratchpadL3Mask;
275273
}
276274

277-
//1 uOP
278275
void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) {
279276
registerUsage[instr.dst] = i;
280277
if(instr.dst == RegisterNeedsDisplacement)
@@ -284,27 +281,18 @@ namespace randomx {
284281
traceint(instr);
285282
}
286283

287-
//2.75 uOP
288284
void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) {
289285
registerUsage[instr.dst] = i;
290286
if (instr.src != instr.dst) {
291287
genAddressReg(instr);
292-
asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
288+
asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
293289
}
294290
else {
295-
asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
291+
asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
296292
}
297293
traceint(instr);
298294
}
299295

300-
//1 uOP
301-
void AssemblyGeneratorX86::h_IADD_RC(Instruction& instr, int i) {
302-
registerUsage[instr.dst] = i;
303-
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
304-
traceint(instr);
305-
}
306-
307-
//1 uOP
308296
void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) {
309297
registerUsage[instr.dst] = i;
310298
if (instr.src != instr.dst) {
@@ -316,27 +304,18 @@ namespace randomx {
316304
traceint(instr);
317305
}
318306

319-
//2.75 uOP
320307
void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) {
321308
registerUsage[instr.dst] = i;
322309
if (instr.src != instr.dst) {
323310
genAddressReg(instr);
324-
asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
311+
asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
325312
}
326313
else {
327-
asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
314+
asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
328315
}
329316
traceint(instr);
330317
}
331318

332-
//1 uOP
333-
void AssemblyGeneratorX86::h_IMUL_9C(Instruction& instr, int i) {
334-
registerUsage[instr.dst] = i;
335-
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.dst] << "*8" << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
336-
traceint(instr);
337-
}
338-
339-
//1 uOP
340319
void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) {
341320
registerUsage[instr.dst] = i;
342321
if (instr.src != instr.dst) {
@@ -348,15 +327,14 @@ namespace randomx {
348327
traceint(instr);
349328
}
350329

351-
//2.75 uOP
352330
void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) {
353331
registerUsage[instr.dst] = i;
354332
if (instr.src != instr.dst) {
355333
genAddressReg(instr);
356-
asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
334+
asmCode << "\timul " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
357335
}
358336
else {
359-
asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
337+
asmCode << "\timul " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
360338
}
361339
traceint(instr);
362340
}
@@ -370,23 +348,21 @@ namespace randomx {
370348
traceint(instr);
371349
}
372350

373-
//5.75 uOPs
374351
void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) {
375352
registerUsage[instr.dst] = i;
376353
if (instr.src != instr.dst) {
377354
genAddressReg(instr, "ecx");
378355
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
379-
asmCode << "\tmul qword ptr [rsi+rcx]" << std::endl;
356+
asmCode << "\tmul qword ptr [" << regScratchpadAddr << "+rcx]" << std::endl;
380357
}
381358
else {
382359
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
383-
asmCode << "\tmul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
360+
asmCode << "\tmul qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
384361
}
385362
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
386363
traceint(instr);
387364
}
388365

389-
//4 uOPs
390366
void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) {
391367
registerUsage[instr.dst] = i;
392368
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
@@ -395,30 +371,27 @@ namespace randomx {
395371
traceint(instr);
396372
}
397373

398-
//5.75 uOPs
399374
void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) {
400375
registerUsage[instr.dst] = i;
401376
if (instr.src != instr.dst) {
402377
genAddressReg(instr, "ecx");
403378
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
404-
asmCode << "\timul qword ptr [rsi+rcx]" << std::endl;
379+
asmCode << "\timul qword ptr [" << regScratchpadAddr << "+rcx]" << std::endl;
405380
}
406381
else {
407382
asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
408-
asmCode << "\timul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
383+
asmCode << "\timul qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
409384
}
410385
asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
411386
traceint(instr);
412387
}
413388

414-
//1 uOP
415389
void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
416390
registerUsage[instr.dst] = i;
417391
asmCode << "\tneg " << regR[instr.dst] << std::endl;
418392
traceint(instr);
419393
}
420394

421-
//1 uOP
422395
void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) {
423396
registerUsage[instr.dst] = i;
424397
if (instr.src != instr.dst) {
@@ -430,20 +403,18 @@ namespace randomx {
430403
traceint(instr);
431404
}
432405

433-
//2.75 uOP
434406
void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) {
435407
registerUsage[instr.dst] = i;
436408
if (instr.src != instr.dst) {
437409
genAddressReg(instr);
438-
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+rax]" << std::endl;
410+
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
439411
}
440412
else {
441-
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
413+
asmCode << "\txor " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl;
442414
}
443415
traceint(instr);
444416
}
445417

446-
//1.75 uOPs
447418
void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) {
448419
registerUsage[instr.dst] = i;
449420
if (instr.src != instr.dst) {
@@ -456,7 +427,6 @@ namespace randomx {
456427
traceint(instr);
457428
}
458429

459-
//1.75 uOPs
460430
void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) {
461431
registerUsage[instr.dst] = i;
462432
if (instr.src != instr.dst) {
@@ -469,7 +439,6 @@ namespace randomx {
469439
traceint(instr);
470440
}
471441

472-
//2 uOPs
473442
void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) {
474443
if (instr.getImm32() != 0) {
475444
registerUsage[instr.dst] = i;
@@ -483,12 +452,6 @@ namespace randomx {
483452
}
484453
}
485454

486-
//~8.5 uOPs
487-
void AssemblyGeneratorX86::h_ISDIV_C(Instruction& instr, int i) {
488-
tracenop(instr);
489-
}
490-
491-
//2 uOPs
492455
void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) {
493456
if (instr.src != instr.dst) {
494457
registerUsage[instr.dst] = i;
@@ -501,100 +464,70 @@ namespace randomx {
501464
}
502465
}
503466

504-
//1 uOPs
505467
void AssemblyGeneratorX86::h_FSWAP_R(Instruction& instr, int i) {
506468
asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl;
507469
traceflt(instr);
508470
}
509471

510-
//1 uOP
511472
void AssemblyGeneratorX86::h_FADD_R(Instruction& instr, int i) {
512473
instr.dst %= 4;
513474
instr.src %= 4;
514475
asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
515476
traceflt(instr);
516477
}
517478

518-
//5 uOPs
519479
void AssemblyGeneratorX86::h_FADD_M(Instruction& instr, int i) {
520480
instr.dst %= 4;
521481
genAddressReg(instr);
522-
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
523-
asmCode << "\taddpd " << regF[instr.dst] << ", xmm12" << std::endl;
482+
asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
483+
asmCode << "\taddpd " << regF[instr.dst] << ", " << tempRegx << std::endl;
524484
traceflt(instr);
525485
}
526486

527-
//1 uOP
528487
void AssemblyGeneratorX86::h_FSUB_R(Instruction& instr, int i) {
529488
instr.dst %= 4;
530489
instr.src %= 4;
531490
asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
532491
traceflt(instr);
533492
}
534493

535-
//5 uOPs
536494
void AssemblyGeneratorX86::h_FSUB_M(Instruction& instr, int i) {
537495
instr.dst %= 4;
538496
genAddressReg(instr);
539-
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
540-
asmCode << "\tsubpd " << regF[instr.dst] << ", xmm12" << std::endl;
497+
asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
498+
asmCode << "\tsubpd " << regF[instr.dst] << ", " << tempRegx << std::endl;
541499
traceflt(instr);
542500
}
543501

544-
//1 uOP
545502
void AssemblyGeneratorX86::h_FSCAL_R(Instruction& instr, int i) {
546503
instr.dst %= 4;
547-
asmCode << "\txorps " << regF[instr.dst] << ", " << signMask << std::endl;
504+
asmCode << "\txorps " << regF[instr.dst] << ", " << scaleMask << std::endl;
548505
traceflt(instr);
549506
}
550507

551-
//1 uOPs
552508
void AssemblyGeneratorX86::h_FMUL_R(Instruction& instr, int i) {
553509
instr.dst %= 4;
554510
instr.src %= 4;
555511
asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
556512
traceflt(instr);
557513
}
558514

559-
//7 uOPs
560-
void AssemblyGeneratorX86::h_FMUL_M(Instruction& instr, int i) {
561-
instr.dst %= 4;
562-
genAddressReg(instr);
563-
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
564-
asmCode << "\tandps xmm12, xmm14" << std::endl;
565-
asmCode << "\tmulpd " << regE[instr.dst] << ", xmm12" << std::endl;
566-
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
567-
traceflt(instr);
568-
}
569-
570-
//2 uOPs
571-
void AssemblyGeneratorX86::h_FDIV_R(Instruction& instr, int i) {
572-
instr.dst %= 4;
573-
instr.src %= 4;
574-
asmCode << "\tdivpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
575-
asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
576-
traceflt(instr);
577-
}
578-
579-
//7 uOPs
580515
void AssemblyGeneratorX86::h_FDIV_M(Instruction& instr, int i) {
581516
instr.dst %= 4;
582517
genAddressReg(instr);
583-
asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
584-
asmCode << "\tandps xmm12, xmm13" << std::endl;
585-
asmCode << "\torps xmm12, xmm14" << std::endl;
586-
asmCode << "\tdivpd " << regE[instr.dst] << ", xmm12" << std::endl;
518+
asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl;
519+
asmCode << "\tandps " << tempRegx << ", " << mantissaMask << std::endl;
520+
asmCode << "\torps " << tempRegx << ", " << exponentMask << std::endl;
521+
asmCode << "\tdivpd " << regE[instr.dst] << ", " << tempRegx << std::endl;
587522
traceflt(instr);
588523
}
589524

590-
//1 uOP
591525
void AssemblyGeneratorX86::h_FSQRT_R(Instruction& instr, int i) {
592526
instr.dst %= 4;
593527
asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl;
594528
traceflt(instr);
595529
}
596530

597-
//6 uOPs
598531
void AssemblyGeneratorX86::h_CFROUND(Instruction& instr, int i) {
599532
asmCode << "\tmov rax, " << regR[instr.src] << std::endl;
600533
int rotate = (13 - (instr.getImm32() & 63)) & 63;
@@ -645,7 +578,6 @@ namespace randomx {
645578
}
646579
}
647580

648-
//4 uOPs
649581
void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
650582
handleCondition(instr, i);
651583
asmCode << "\txor ecx, ecx" << std::endl;
@@ -655,28 +587,9 @@ namespace randomx {
655587
traceint(instr);
656588
}
657589

658-
//6 uOPs
659-
void AssemblyGeneratorX86::h_COND_M(Instruction& instr, int i) {
660-
handleCondition(instr, i);
661-
asmCode << "\txor ecx, ecx" << std::endl;
662-
genAddressReg(instr);
663-
asmCode << "\tcmp dword ptr [rsi+rax], " << (int32_t)instr.getImm32() << std::endl;
664-
asmCode << "\tset" << condition(instr) << " cl" << std::endl;
665-
asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
666-
traceint(instr);
667-
}
668-
669-
//3 uOPs
670590
void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
671591
genAddressRegDst(instr);
672-
asmCode << "\tmov qword ptr [rsi+rax], " << regR[instr.src] << std::endl;
673-
tracenop(instr);
674-
}
675-
676-
//3 uOPs
677-
void AssemblyGeneratorX86::h_FSTORE(Instruction& instr, int i) {
678-
genAddressRegDst(instr, 16);
679-
asmCode << "\tmovapd xmmword ptr [rsi+rax], " << regFE[instr.src] << std::endl;
592+
asmCode << "\tmov qword ptr [" << regScratchpadAddr << "+rax], " << regR[instr.src] << std::endl;
680593
tracenop(instr);
681594
}
682595

@@ -692,10 +605,8 @@ namespace randomx {
692605
//Integer
693606
INST_HANDLE(IADD_RS)
694607
INST_HANDLE(IADD_M)
695-
INST_HANDLE(IADD_RC)
696608
INST_HANDLE(ISUB_R)
697609
INST_HANDLE(ISUB_M)
698-
INST_HANDLE(IMUL_9C)
699610
INST_HANDLE(IMUL_R)
700611
INST_HANDLE(IMUL_M)
701612
INST_HANDLE(IMULH_R)
@@ -727,7 +638,6 @@ namespace randomx {
727638

728639
//Control
729640
INST_HANDLE(COND_R)
730-
INST_HANDLE(COND_M)
731641
INST_HANDLE(CFROUND)
732642
INST_HANDLE(ISTORE)
733643

‎src/assembly_generator_x86.hpp

-6
Original file line numberDiff line numberDiff line change
@@ -50,10 +50,8 @@ namespace randomx {
5050
void tracenop(Instruction&);
5151
void h_IADD_RS(Instruction&, int);
5252
void h_IADD_M(Instruction&, int);
53-
void h_IADD_RC(Instruction&, int);
5453
void h_ISUB_R(Instruction&, int);
5554
void h_ISUB_M(Instruction&, int);
56-
void h_IMUL_9C(Instruction&, int);
5755
void h_IMUL_R(Instruction&, int);
5856
void h_IMUL_M(Instruction&, int);
5957
void h_IMULH_R(Instruction&, int);
@@ -75,15 +73,11 @@ namespace randomx {
7573
void h_FSUB_M(Instruction&, int);
7674
void h_FSCAL_R(Instruction&, int);
7775
void h_FMUL_R(Instruction&, int);
78-
void h_FMUL_M(Instruction&, int);
79-
void h_FDIV_R(Instruction&, int);
8076
void h_FDIV_M(Instruction&, int);
8177
void h_FSQRT_R(Instruction&, int);
8278
void h_COND_R(Instruction&, int);
83-
void h_COND_M(Instruction&, int);
8479
void h_CFROUND(Instruction&, int);
8580
void h_ISTORE(Instruction&, int);
86-
void h_FSTORE(Instruction&, int);
8781
void h_NOP(Instruction&, int);
8882

8983
static InstructionGenerator engine[256];

‎src/common.hpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -40,13 +40,13 @@ namespace randomx {
4040
static_assert((RANDOMX_SCRATCHPAD_L1 & (RANDOMX_SCRATCHPAD_L1 - 1)) == 0, "RANDOMX_SCRATCHPAD_L1 must be a power of 2.");
4141
static_assert(RANDOMX_CACHE_ACCESSES > 1, "RANDOMX_CACHE_ACCESSES must be greater than 1");
4242

43-
constexpr int wtSum = RANDOMX_FREQ_IADD_RS + RANDOMX_FREQ_IADD_M + RANDOMX_FREQ_IADD_RC + RANDOMX_FREQ_ISUB_R + \
44-
RANDOMX_FREQ_ISUB_M + RANDOMX_FREQ_IMUL_9C + RANDOMX_FREQ_IMUL_R + RANDOMX_FREQ_IMUL_M + RANDOMX_FREQ_IMULH_R + \
43+
constexpr int wtSum = RANDOMX_FREQ_IADD_RS + RANDOMX_FREQ_IADD_M + RANDOMX_FREQ_ISUB_R + \
44+
RANDOMX_FREQ_ISUB_M + RANDOMX_FREQ_IMUL_R + RANDOMX_FREQ_IMUL_M + RANDOMX_FREQ_IMULH_R + \
4545
RANDOMX_FREQ_IMULH_M + RANDOMX_FREQ_ISMULH_R + RANDOMX_FREQ_ISMULH_M + RANDOMX_FREQ_IMUL_RCP + \
4646
RANDOMX_FREQ_INEG_R + RANDOMX_FREQ_IXOR_R + RANDOMX_FREQ_IXOR_M + RANDOMX_FREQ_IROR_R + RANDOMX_FREQ_ISWAP_R + \
4747
RANDOMX_FREQ_FSWAP_R + RANDOMX_FREQ_FADD_R + RANDOMX_FREQ_FADD_M + RANDOMX_FREQ_FSUB_R + RANDOMX_FREQ_FSUB_M + \
4848
RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R + RANDOMX_FREQ_COND_R + \
49-
RANDOMX_FREQ_COND_M + RANDOMX_FREQ_CFROUND + RANDOMX_FREQ_ISTORE + RANDOMX_FREQ_NOP;
49+
RANDOMX_FREQ_CFROUND + RANDOMX_FREQ_ISTORE + RANDOMX_FREQ_NOP;
5050

5151
static_assert(wtSum == 256, "Sum of instruction frequencies must be 256.");
5252

‎src/configuration.h

-3
Original file line numberDiff line numberDiff line change
@@ -68,10 +68,8 @@ Total sum of frequencies must be 256
6868

6969
#define RANDOMX_FREQ_IADD_RS 32
7070
#define RANDOMX_FREQ_IADD_M 7
71-
#define RANDOMX_FREQ_IADD_RC 0
7271
#define RANDOMX_FREQ_ISUB_R 17
7372
#define RANDOMX_FREQ_ISUB_M 7
74-
#define RANDOMX_FREQ_IMUL_9C 0
7573
#define RANDOMX_FREQ_IMUL_R 16
7674
#define RANDOMX_FREQ_IMUL_M 4
7775
#define RANDOMX_FREQ_IMULH_R 4
@@ -97,7 +95,6 @@ Total sum of frequencies must be 256
9795
#define RANDOMX_FREQ_FSQRT_R 6
9896

9997
#define RANDOMX_FREQ_COND_R 8
100-
#define RANDOMX_FREQ_COND_M 0
10198
#define RANDOMX_FREQ_CFROUND 1
10299
#define RANDOMX_FREQ_ISTORE 16
103100

‎src/instruction.cpp

-47
Original file line numberDiff line numberDiff line change
@@ -65,10 +65,6 @@ namespace randomx {
6565
}
6666
}
6767

68-
void Instruction::h_IADD_RC(std::ostream& os) const {
69-
os << "r" << (int)dst << ", r" << (int)src << ", " << (int32_t)getImm32() << std::endl;
70-
}
71-
7268
//1 uOP
7369
void Instruction::h_ISUB_R(std::ostream& os) const {
7470
if (src != dst) {
@@ -92,10 +88,6 @@ namespace randomx {
9288
}
9389
}
9490

95-
void Instruction::h_IMUL_9C(std::ostream& os) const {
96-
os << "r" << (int)dst << ", " << (int32_t)getImm32() << std::endl;
97-
}
98-
9991
void Instruction::h_IMUL_R(std::ostream& os) const {
10092
if (src != dst) {
10193
os << "r" << (int)dst << ", r" << (int)src << std::endl;
@@ -200,10 +192,6 @@ namespace randomx {
200192
os << "r" << (int)dst << ", " << getImm32() << std::endl;
201193
}
202194

203-
void Instruction::h_ISDIV_C(std::ostream& os) const {
204-
os << "r" << (int)dst << ", " << (int32_t)getImm32() << std::endl;
205-
}
206-
207195
void Instruction::h_ISWAP_R(std::ostream& os) const {
208196
os << "r" << (int)dst << ", r" << (int)src << std::endl;
209197
}
@@ -251,19 +239,6 @@ namespace randomx {
251239
os << "e" << dstIndex << ", a" << srcIndex << std::endl;
252240
}
253241

254-
void Instruction::h_FMUL_M(std::ostream& os) const {
255-
auto dstIndex = dst % 4;
256-
os << "e" << dstIndex << ", ";
257-
genAddressReg(os);
258-
os << std::endl;
259-
}
260-
261-
void Instruction::h_FDIV_R(std::ostream& os) const {
262-
auto dstIndex = dst % 4;
263-
auto srcIndex = src % 4;
264-
os << "e" << dstIndex << ", a" << srcIndex << std::endl;
265-
}
266-
267242
void Instruction::h_FDIV_M(std::ostream& os) const {
268243
auto dstIndex = dst % 4;
269244
os << "e" << dstIndex << ", ";
@@ -308,24 +283,11 @@ namespace randomx {
308283
os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(r" << (int)src << ", " << (int32_t)getImm32() << "), LSH " << (int)(mod >> 5) << std::endl;
309284
}
310285

311-
void Instruction::h_COND_M(std::ostream& os) const {
312-
os << "r" << (int)dst << ", " << condition((mod >> 2) & 7) << "(";
313-
genAddressReg(os);
314-
os << ", " << (int32_t)getImm32() << "), LSH " << (int)(mod >> 5) << std::endl;
315-
}
316-
317286
void Instruction::h_ISTORE(std::ostream& os) const {
318287
genAddressRegDst(os);
319288
os << ", r" << (int)src << std::endl;
320289
}
321290

322-
void Instruction::h_FSTORE(std::ostream& os) const {
323-
const char reg = (src >= 4) ? 'e' : 'f';
324-
genAddressRegDst(os);
325-
auto srcIndex = src % 4;
326-
os << ", " << reg << srcIndex << std::endl;
327-
}
328-
329291
void Instruction::h_NOP(std::ostream& os) const {
330292
os << std::endl;
331293
}
@@ -338,10 +300,8 @@ namespace randomx {
338300
//Integer
339301
INST_NAME(IADD_RS)
340302
INST_NAME(IADD_M)
341-
INST_NAME(IADD_RC)
342303
INST_NAME(ISUB_R)
343304
INST_NAME(ISUB_M)
344-
INST_NAME(IMUL_9C)
345305
INST_NAME(IMUL_R)
346306
INST_NAME(IMUL_M)
347307
INST_NAME(IMULH_R)
@@ -372,7 +332,6 @@ namespace randomx {
372332

373333
//Control
374334
INST_NAME(COND_R)
375-
INST_NAME(COND_M)
376335
INST_NAME(CFROUND)
377336

378337
INST_NAME(ISTORE)
@@ -384,10 +343,8 @@ namespace randomx {
384343
//Integer
385344
INST_HANDLE(IADD_RS)
386345
INST_HANDLE(IADD_M)
387-
INST_HANDLE(IADD_RC)
388346
INST_HANDLE(ISUB_R)
389347
INST_HANDLE(ISUB_M)
390-
INST_HANDLE(IMUL_9C)
391348
INST_HANDLE(IMUL_R)
392349
INST_HANDLE(IMUL_M)
393350
INST_HANDLE(IMULH_R)
@@ -417,13 +374,9 @@ namespace randomx {
417374
INST_HANDLE(FDIV_M)
418375
INST_HANDLE(FSQRT_R)
419376

420-
//Control
421377
INST_HANDLE(COND_R)
422-
INST_HANDLE(COND_M)
423378
INST_HANDLE(CFROUND)
424-
425379
INST_HANDLE(ISTORE)
426-
427380
INST_HANDLE(NOP)
428381
};
429382

‎src/instruction.hpp

+28-39
Original file line numberDiff line numberDiff line change
@@ -32,38 +32,34 @@ namespace randomx {
3232
namespace InstructionType {
3333
constexpr int IADD_RS = 0;
3434
constexpr int IADD_M = 1;
35-
constexpr int IADD_RC = 2;
36-
constexpr int ISUB_R = 3;
37-
constexpr int ISUB_M = 4;
38-
constexpr int IMUL_9C = 5;
39-
constexpr int IMUL_R = 6;
40-
constexpr int IMUL_M = 7;
41-
constexpr int IMULH_R = 8;
42-
constexpr int IMULH_M = 9;
43-
constexpr int ISMULH_R = 10;
44-
constexpr int ISMULH_M = 11;
45-
constexpr int IMUL_RCP = 12;
46-
constexpr int INEG_R = 13;
47-
constexpr int IXOR_R = 14;
48-
constexpr int IXOR_M = 15;
49-
constexpr int IROR_R = 16;
50-
constexpr int IROL_R = 17;
51-
constexpr int ISWAP_R = 18;
52-
constexpr int FSWAP_R = 19;
53-
constexpr int FADD_R = 20;
54-
constexpr int FADD_M = 21;
55-
constexpr int FSUB_R = 22;
56-
constexpr int FSUB_M = 23;
57-
constexpr int FSCAL_R = 24;
58-
constexpr int FMUL_R = 25;
59-
constexpr int FDIV_M = 26;
60-
constexpr int FSQRT_R = 27;
61-
constexpr int COND_R = 28;
62-
constexpr int COND_M = 29;
63-
constexpr int CFROUND = 30;
64-
constexpr int ISTORE = 31;
65-
constexpr int FSTORE = 32;
66-
constexpr int NOP = 33;
35+
constexpr int ISUB_R = 2;
36+
constexpr int ISUB_M = 3;
37+
constexpr int IMUL_R = 4;
38+
constexpr int IMUL_M = 5;
39+
constexpr int IMULH_R = 6;
40+
constexpr int IMULH_M = 7;
41+
constexpr int ISMULH_R = 8;
42+
constexpr int ISMULH_M = 9;
43+
constexpr int IMUL_RCP = 10;
44+
constexpr int INEG_R = 11;
45+
constexpr int IXOR_R = 12;
46+
constexpr int IXOR_M = 13;
47+
constexpr int IROR_R = 14;
48+
constexpr int IROL_R = 15;
49+
constexpr int ISWAP_R = 16;
50+
constexpr int FSWAP_R = 17;
51+
constexpr int FADD_R = 18;
52+
constexpr int FADD_M = 19;
53+
constexpr int FSUB_R = 20;
54+
constexpr int FSUB_M = 21;
55+
constexpr int FSCAL_R = 22;
56+
constexpr int FMUL_R = 23;
57+
constexpr int FDIV_M = 24;
58+
constexpr int FSQRT_R = 25;
59+
constexpr int COND_R = 26;
60+
constexpr int CFROUND = 27;
61+
constexpr int ISTORE = 28;
62+
constexpr int NOP = 29;
6763
}
6864

6965
class Instruction {
@@ -112,18 +108,15 @@ namespace randomx {
112108
void genAddressRegDst(std::ostream&) const;
113109
void h_IADD_RS(std::ostream&) const;
114110
void h_IADD_M(std::ostream&) const;
115-
void h_IADD_RC(std::ostream&) const;
116111
void h_ISUB_R(std::ostream&) const;
117112
void h_ISUB_M(std::ostream&) const;
118-
void h_IMUL_9C(std::ostream&) const;
119113
void h_IMUL_R(std::ostream&) const;
120114
void h_IMUL_M(std::ostream&) const;
121115
void h_IMULH_R(std::ostream&) const;
122116
void h_IMULH_M(std::ostream&) const;
123117
void h_ISMULH_R(std::ostream&) const;
124118
void h_ISMULH_M(std::ostream&) const;
125119
void h_IMUL_RCP(std::ostream&) const;
126-
void h_ISDIV_C(std::ostream&) const;
127120
void h_INEG_R(std::ostream&) const;
128121
void h_IXOR_R(std::ostream&) const;
129122
void h_IXOR_M(std::ostream&) const;
@@ -137,15 +130,11 @@ namespace randomx {
137130
void h_FSUB_M(std::ostream&) const;
138131
void h_FSCAL_R(std::ostream&) const;
139132
void h_FMUL_R(std::ostream&) const;
140-
void h_FMUL_M(std::ostream&) const;
141-
void h_FDIV_R(std::ostream&) const;
142133
void h_FDIV_M(std::ostream&) const;
143134
void h_FSQRT_R(std::ostream&) const;
144135
void h_COND_R(std::ostream&) const;
145-
void h_COND_M(std::ostream&) const;
146136
void h_CFROUND(std::ostream&) const;
147137
void h_ISTORE(std::ostream&) const;
148-
void h_FSTORE(std::ostream&) const;
149138
void h_NOP(std::ostream&) const;
150139
};
151140

‎src/instructions_portable.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
1919

2020
//#define DEBUG
2121

22-
#pragma STDC FENV_ACCESS on
22+
#pragma STDC FENV_ACCESS ON
2323
#include <cfenv>
2424
#include <cmath>
2525
#ifdef DEBUG

‎src/jit_compiler_x86.cpp

-3
Original file line numberDiff line numberDiff line change
@@ -953,10 +953,8 @@ namespace randomx {
953953
InstructionGeneratorX86 JitCompilerX86::engine[256] = {
954954
INST_HANDLE(IADD_RS)
955955
INST_HANDLE(IADD_M)
956-
INST_HANDLE(IADD_RC)
957956
INST_HANDLE(ISUB_R)
958957
INST_HANDLE(ISUB_M)
959-
INST_HANDLE(IMUL_9C)
960958
INST_HANDLE(IMUL_R)
961959
INST_HANDLE(IMUL_M)
962960
INST_HANDLE(IMULH_R)
@@ -980,7 +978,6 @@ namespace randomx {
980978
INST_HANDLE(FDIV_M)
981979
INST_HANDLE(FSQRT_R)
982980
INST_HANDLE(COND_R)
983-
INST_HANDLE(COND_M)
984981
INST_HANDLE(CFROUND)
985982
INST_HANDLE(ISTORE)
986983
INST_HANDLE(NOP)

‎src/vm_interpreted.cpp

-57
Original file line numberDiff line numberDiff line change
@@ -125,10 +125,6 @@ namespace randomx {
125125
*ibc.idst += load64(getScratchpadAddress(ibc));
126126
} break;
127127

128-
case InstructionType::IADD_RC: {
129-
*ibc.idst += *ibc.isrc + ibc.imm;
130-
} break;
131-
132128
case InstructionType::ISUB_R: {
133129
*ibc.idst -= *ibc.isrc;
134130
} break;
@@ -137,10 +133,6 @@ namespace randomx {
137133
*ibc.idst -= load64(getScratchpadAddress(ibc));
138134
} break;
139135

140-
case InstructionType::IMUL_9C: {
141-
*ibc.idst += 8 * *ibc.idst + ibc.imm;
142-
} break;
143-
144136
case InstructionType::IMUL_R: { //also handles IMUL_RCP
145137
*ibc.idst *= *ibc.isrc;
146138
} break;
@@ -243,18 +235,6 @@ namespace randomx {
243235
*ibc.idst += condition(ibc.condition, *ibc.isrc, ibc.imm) ? 1 : 0;
244236
} break;
245237

246-
case InstructionType::COND_M: {
247-
#ifdef RANDOMX_JUMP
248-
*ibc.creg += (1uLL << ibc.shift);
249-
const uint64_t conditionMask = ((1ULL << RANDOMX_CONDITION_BITS) - 1) << ibc.shift;
250-
if ((*ibc.creg & conditionMask) == 0) {
251-
ic = ibc.target;
252-
break;
253-
}
254-
#endif
255-
*ibc.idst += condition(ibc.condition, load64(getScratchpadAddress(ibc)), ibc.imm) ? 1 : 0;
256-
} break;
257-
258238
case InstructionType::CFROUND: {
259239
setRoundMode(rotr(*ibc.isrc, ibc.imm) % 4);
260240
} break;
@@ -482,16 +462,6 @@ namespace randomx {
482462
registerUsage[instr.dst] = i;
483463
} break;
484464

485-
CASE_REP(IADD_RC) {
486-
auto dst = instr.dst % RegistersCount;
487-
auto src = instr.src % RegistersCount;
488-
ibc.type = InstructionType::IADD_RC;
489-
ibc.idst = &r[dst];
490-
ibc.isrc = &r[src];
491-
ibc.imm = signExtend2sCompl(instr.getImm32());
492-
registerUsage[instr.dst] = i;
493-
} break;
494-
495465
CASE_REP(ISUB_R) {
496466
auto dst = instr.dst % RegistersCount;
497467
auto src = instr.src % RegistersCount;
@@ -524,14 +494,6 @@ namespace randomx {
524494
registerUsage[instr.dst] = i;
525495
} break;
526496

527-
CASE_REP(IMUL_9C) {
528-
auto dst = instr.dst % RegistersCount;
529-
ibc.type = InstructionType::IMUL_9C;
530-
ibc.idst = &r[dst];
531-
ibc.imm = signExtend2sCompl(instr.getImm32());
532-
registerUsage[instr.dst] = i;
533-
} break;
534-
535497
CASE_REP(IMUL_R) {
536498
auto dst = instr.dst % RegistersCount;
537499
auto src = instr.src % RegistersCount;
@@ -808,25 +770,6 @@ namespace randomx {
808770
}
809771
} break;
810772

811-
CASE_REP(COND_M) {
812-
auto dst = instr.dst % RegistersCount;
813-
auto src = instr.src % RegistersCount;
814-
ibc.type = InstructionType::COND_M;
815-
ibc.idst = &r[dst];
816-
ibc.isrc = &r[src];
817-
ibc.condition = instr.getModCond();
818-
ibc.imm = instr.getImm32();
819-
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
820-
//jump condition
821-
int reg = getConditionRegister(registerUsage);
822-
ibc.target = registerUsage[reg];
823-
ibc.shift = instr.getModShift3();
824-
ibc.creg = &r[reg];
825-
for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
826-
registerUsage[j] = i;
827-
}
828-
} break;
829-
830773
CASE_REP(CFROUND) {
831774
auto src = instr.src % 8;
832775
ibc.isrc = &r[src];

‎src/vm_interpreted_light.hpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ namespace randomx {
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void setDataset(randomx_dataset* dataset) override { }
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void setCache(randomx_cache* cache) override;
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protected:
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virtual void datasetRead(uint32_t address, int_reg_t(&r)[8]);
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void datasetRead(uint32_t address, int_reg_t(&r)[8]) override;
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private:
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randomx_cache* cachePtr;
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};

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