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Commit fd7186f

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tevadortevador
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Changed IADD_RS to use mod.mem
1 parent ff88a57 commit fd7186f

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8 files changed

+43
-47
lines changed

8 files changed

+43
-47
lines changed

‎doc/program.asm‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ randomx_isn_14:
5656
sqrtpd xmm6, xmm6
5757
randomx_isn_15:
5858
; IADD_RS r6, r2, LSH 1
59-
lea r14, [r14+r10*8]
59+
lea r14, [r14+r10*2]
6060
randomx_isn_16:
6161
; FSUB_M f2, L1[r1-1890725713]
6262
lea eax, [r9d-1890725713]
@@ -145,7 +145,7 @@ randomx_isn_35:
145145
imul r14, 835132161
146146
randomx_isn_36:
147147
; IADD_RS r3, r4, LSH 2
148-
lea r11, [r11+r12*2]
148+
lea r11, [r11+r12*4]
149149
randomx_isn_37:
150150
; ISUB_M r6, L2[r4+1885029796]
151151
lea eax, [r12d+1885029796]
@@ -179,7 +179,7 @@ randomx_isn_45:
179179
mov qword ptr [rsi+rax], r13
180180
randomx_isn_46:
181181
; IADD_RS r0, r7, LSH 0
182-
lea r8, [r8+r15*8]
182+
lea r8, [r8+r15*1]
183183
randomx_isn_47:
184184
; IXOR_R r5, r2
185185
xor r13, r10
@@ -227,7 +227,7 @@ randomx_isn_57:
227227
imul r13, r9
228228
randomx_isn_58:
229229
; IADD_RS r5, r1, -999103579, LSH 0
230-
lea r13, [r13+r9*8-999103579]
230+
lea r13, [r13+r9*1-999103579]
231231
randomx_isn_59:
232232
; FMUL_R e2, a2
233233
mulpd xmm6, xmm10
@@ -237,7 +237,7 @@ randomx_isn_60:
237237
ror r10, cl
238238
randomx_isn_61:
239239
; IADD_RS r0, r3, LSH 1
240-
lea r8, [r8+r11*1]
240+
lea r8, [r8+r11*2]
241241
randomx_isn_62:
242242
; FSQRT_R e3
243243
sqrtpd xmm7, xmm7
@@ -260,7 +260,7 @@ randomx_isn_66:
260260
sub r12, 841292629
261261
randomx_isn_67:
262262
; IADD_RS r4, r6, LSH 2
263-
lea r12, [r12+r14*1]
263+
lea r12, [r12+r14*4]
264264
randomx_isn_68:
265265
; FSUB_M f3, L1[r4+613549729]
266266
lea eax, [r12d+613549729]
@@ -427,7 +427,7 @@ randomx_isn_107:
427427
mov r14, rdx
428428
randomx_isn_108:
429429
; IADD_RS r7, r0, LSH 1
430-
lea r15, [r15+r8*4]
430+
lea r15, [r15+r8*2]
431431
randomx_isn_109:
432432
; IMUL_R r6, r5
433433
imul r14, r13
@@ -442,13 +442,13 @@ randomx_isn_111:
442442
addpd xmm2, xmm12
443443
randomx_isn_112:
444444
; IADD_RS r0, r3, LSH 0
445-
lea r8, [r8+r11*2]
445+
lea r8, [r8+r11*1]
446446
randomx_isn_113:
447447
; IADD_RS r3, r4, LSH 1
448448
lea r11, [r11+r12*2]
449449
randomx_isn_114:
450450
; IADD_RS r2, r4, LSH 2
451-
lea r10, [r10+r12*8]
451+
lea r10, [r10+r12*4]
452452
randomx_isn_115:
453453
; IMUL_M r7, L1[r2-106928748]
454454
lea eax, [r10d-106928748]
@@ -462,7 +462,7 @@ randomx_isn_117:
462462
subpd xmm2, xmm10
463463
randomx_isn_118:
464464
; IADD_RS r2, r2, LSH 0
465-
lea r10, [r10+r10*2]
465+
lea r10, [r10+r10*1]
466466
randomx_isn_119:
467467
; ISUB_R r7, -342152774
468468
sub r15, -342152774
@@ -471,7 +471,7 @@ randomx_isn_120:
471471
lea r12, [r12+r9*2]
472472
randomx_isn_121:
473473
; IADD_RS r4, r7, LSH 2
474-
lea r12, [r12+r15*1]
474+
lea r12, [r12+r15*4]
475475
randomx_isn_122:
476476
; FSUB_R f0, a1
477477
subpd xmm0, xmm9
@@ -502,7 +502,7 @@ randomx_isn_128:
502502
subpd xmm3, xmm9
503503
randomx_isn_129:
504504
; IADD_RS r1, r2, LSH 2
505-
lea r9, [r9+r10*2]
505+
lea r9, [r9+r10*4]
506506
randomx_isn_130:
507507
; FSUB_R f1, a1
508508
subpd xmm1, xmm9
@@ -529,7 +529,7 @@ randomx_isn_136:
529529
sub r11, r14
530530
randomx_isn_137:
531531
; IADD_RS r4, r1, LSH 0
532-
lea r12, [r12+r9*8]
532+
lea r12, [r12+r9*1]
533533
randomx_isn_138:
534534
; ISTORE L1[r0+56684410], r0
535535
lea eax, [r8d+56684410]
@@ -571,10 +571,10 @@ randomx_isn_145:
571571
sub r13, r11
572572
randomx_isn_146:
573573
; IADD_RS r0, r3, LSH 1
574-
lea r8, [r8+r11*4]
574+
lea r8, [r8+r11*2]
575575
randomx_isn_147:
576576
; IADD_RS r1, r3, LSH 1
577-
lea r9, [r9+r11*1]
577+
lea r9, [r9+r11*2]
578578
randomx_isn_148:
579579
; FSQRT_R e1
580580
sqrtpd xmm5, xmm5
@@ -623,7 +623,7 @@ randomx_isn_158:
623623
mov qword ptr [rsi+rax], r12
624624
randomx_isn_159:
625625
; IADD_RS r7, r2, LSH 3
626-
lea r15, [r15+r10*4]
626+
lea r15, [r15+r10*8]
627627
randomx_isn_160:
628628
; IMUL_RCP r7, 2040763167
629629
mov rax, 9705702723791900149
@@ -715,7 +715,7 @@ randomx_isn_182:
715715
mulpd xmm6, xmm10
716716
randomx_isn_183:
717717
; IADD_RS r6, r2, LSH 0
718-
lea r14, [r14+r10*8]
718+
lea r14, [r14+r10*1]
719719
randomx_isn_184:
720720
; FADD_R f2, a3
721721
addpd xmm2, xmm11
@@ -727,7 +727,7 @@ randomx_isn_186:
727727
xorps xmm3, xmm15
728728
randomx_isn_187:
729729
; IADD_RS r6, r6, LSH 3
730-
lea r14, [r14+r14*4]
730+
lea r14, [r14+r14*8]
731731
randomx_isn_188:
732732
; FSCAL_R f2
733733
xorps xmm2, xmm15
@@ -780,7 +780,7 @@ randomx_isn_199:
780780
subpd xmm3, xmm11
781781
randomx_isn_200:
782782
; IADD_RS r2, r5, LSH 2
783-
lea r10, [r10+r13*1]
783+
lea r10, [r10+r13*4]
784784
randomx_isn_201:
785785
; ISUB_M r6, L2[r3+376384700]
786786
lea eax, [r11d+376384700]
@@ -810,7 +810,7 @@ randomx_isn_207:
810810
xorps xmm1, xmm15
811811
randomx_isn_208:
812812
; IADD_RS r6, r3, LSH 1
813-
lea r14, [r14+r11*1]
813+
lea r14, [r14+r11*2]
814814
randomx_isn_209:
815815
; FSUB_M f0, L1[r4-557177119]
816816
lea eax, [r12d-557177119]
@@ -873,7 +873,7 @@ randomx_isn_223:
873873
xorps xmm2, xmm15
874874
randomx_isn_224:
875875
; IADD_RS r5, r4, 312567979, LSH 1
876-
lea r13, [r13+r12*4+312567979]
876+
lea r13, [r13+r12*2+312567979]
877877
randomx_isn_225:
878878
; ISTORE L2[r2+260885699], r1
879879
lea eax, [r10d+260885699]
@@ -898,7 +898,7 @@ randomx_isn_229:
898898
xchg r8, r14
899899
randomx_isn_230:
900900
; IADD_RS r2, r7, LSH 2
901-
lea r10, [r10+r15*1]
901+
lea r10, [r10+r15*4]
902902
randomx_isn_231:
903903
; FMUL_R e1, a0
904904
mulpd xmm5, xmm8
@@ -924,7 +924,7 @@ randomx_isn_237:
924924
subpd xmm1, xmm11
925925
randomx_isn_238:
926926
; IADD_RS r4, r2, LSH 1
927-
lea r12, [r12+r10*4]
927+
lea r12, [r12+r10*2]
928928
randomx_isn_239:
929929
; IMUL_RCP r7, 3065786637
930930
mov rax, 12921343181238534701
@@ -978,13 +978,13 @@ randomx_isn_250:
978978
addpd xmm3, xmm8
979979
randomx_isn_251:
980980
; IADD_RS r0, r0, LSH 0
981-
lea r8, [r8+r8*4]
981+
lea r8, [r8+r8*1]
982982
randomx_isn_252:
983983
; ISUB_R r4, r2
984984
sub r12, r10
985985
randomx_isn_253:
986986
; IADD_RS r5, r4, 256175395, LSH 0
987-
lea r13, [r13+r12*4+256175395]
987+
lea r13, [r13+r12*1+256175395]
988988
randomx_isn_254:
989989
; IADD_RS r6, r7, LSH 2
990990
lea r14, [r14+r15*4]

‎src/assembly_generator_x86.cpp‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ namespace randomx {
7171
asmCode << "xor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
7272
break;
7373
case SuperscalarInstructionType::IADD_RS:
74-
asmCode << "lea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << "]" << std::endl;
74+
asmCode << "lea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << "]" << std::endl;
7575
break;
7676
case SuperscalarInstructionType::IMUL_R:
7777
asmCode << "imul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
@@ -180,7 +180,7 @@ namespace randomx {
180180
asmCode << regR[instr.dst] << " ^= " << regR[instr.src] << ";" << std::endl;
181181
break;
182182
case SuperscalarInstructionType::IADD_RS:
183-
asmCode << regR[instr.dst] << " += " << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << ";" << std::endl;
183+
asmCode << regR[instr.dst] << " += " << regR[instr.src] << "*" << (1 << (instr.getModMem())) << ";" << std::endl;
184184
break;
185185
case SuperscalarInstructionType::IMUL_R:
186186
asmCode << regR[instr.dst] << " *= " << regR[instr.src] << ";" << std::endl;
@@ -275,9 +275,9 @@ namespace randomx {
275275
void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) {
276276
registerUsage[instr.dst] = i;
277277
if(instr.dst == RegisterNeedsDisplacement)
278-
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
278+
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
279279
else
280-
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift2())) << "]" << std::endl;
280+
asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << "]" << std::endl;
281281
traceint(instr);
282282
}
283283

@@ -442,7 +442,6 @@ namespace randomx {
442442
void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) {
443443
if (instr.getImm32() != 0) {
444444
registerUsage[instr.dst] = i;
445-
uint32_t divisor = instr.getImm32();
446445
asmCode << "\tmov rax, " << randomx_reciprocal(instr.getImm32()) << std::endl;
447446
asmCode << "\timul " << regR[instr.dst] << ", rax" << std::endl;
448447
traceint(instr);
@@ -566,7 +565,7 @@ namespace randomx {
566565
}
567566

568567
void AssemblyGeneratorX86::handleCondition(Instruction& instr, int i) {
569-
const int shift = instr.getModShift3();
568+
const int shift = instr.getModShift();
570569
const int conditionMask = ((1 << RANDOMX_CONDITION_BITS) - 1) << shift;
571570
int reg = getConditionRegister();
572571
int target = registerUsage[reg] + 1;

‎src/configuration.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
3131
//Argon2d salt
3232
#define RANDOMX_ARGON_SALT "RandomX\x03"
3333

34-
//Number of random Cache accesses per Dataset block. Minimum is 2.
34+
//Number of random Cache accesses per Dataset item. Minimum is 2.
3535
#define RANDOMX_CACHE_ACCESSES 8
3636

3737
#define RANDOMX_SUPERSCALAR_LATENCY 170

‎src/instruction.hpp‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -78,16 +78,13 @@ namespace randomx {
7878
return os;
7979
}
8080
int getModMem() const {
81-
return mod % 4;
81+
return mod % 4; //bits 0-1
8282
}
8383
int getModCond() const {
84-
return (mod >> 2) & 7;
84+
return (mod >> 2) % 8; //bits 2-4
8585
}
86-
int getModShift3() const {
87-
return mod >> 5;
88-
}
89-
int getModShift2() const {
90-
return mod >> 6;
86+
int getModShift() const {
87+
return mod >> 5; //bits 5-7
9188
}
9289
void setMod(uint8_t val) {
9390
mod = val;

‎src/jit_compiler_x86.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,7 @@ namespace randomx {
357357
case randomx::SuperscalarInstructionType::IADD_RS:
358358
emit(REX_LEA);
359359
emitByte(0x04 + 8 * instr.dst);
360-
genSIB(instr.getModShift2(), instr.src, instr.dst);
360+
genSIB(instr.getModMem(), instr.src, instr.dst);
361361
break;
362362
case randomx::SuperscalarInstructionType::IMUL_R:
363363
emit(REX_IMUL_RR);
@@ -481,7 +481,7 @@ namespace randomx {
481481
emitByte(0xac);
482482
else
483483
emitByte(0x04 + 8 * instr.dst);
484-
genSIB(instr.getModShift2(), instr.src, instr.dst);
484+
genSIB(instr.getModMem(), instr.src, instr.dst);
485485
if (instr.dst == RegisterNeedsDisplacement)
486486
emit32(instr.getImm32());
487487
}
@@ -882,7 +882,7 @@ namespace randomx {
882882
}
883883

884884
void JitCompilerX86::handleCondition(Instruction& instr, int i) {
885-
const int shift = instr.getModShift3();
885+
const int shift = instr.getModShift();
886886
const int conditionMask = ((1 << RANDOMX_CONDITION_BITS) - 1) << shift;
887887
int reg = getConditionRegister();
888888
int target = registerUsage[reg] + 1;

‎src/superscalar.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -849,7 +849,7 @@ namespace randomx {
849849
r[instr.dst] ^= r[instr.src];
850850
break;
851851
case randomx::SuperscalarInstructionType::IADD_RS:
852-
r[instr.dst] += r[instr.src] << instr.getModShift2();
852+
r[instr.dst] += r[instr.src] << instr.getModMem();
853853
break;
854854
case randomx::SuperscalarInstructionType::IMUL_R:
855855
r[instr.dst] *= r[instr.src];

‎src/tests/benchmark.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ int main(int argc, char** argv) {
225225
std::cout << "Calculated result: ";
226226
result.print(std::cout);
227227
if (noncesCount == 1000 && seedValue == 0)
228-
std::cout << "Reference result: 918a8bc3ce0e537eec9d3c5e1a8bb3204ae3954f14c50c14810b38e49588a9e0" << std::endl;
228+
std::cout << "Reference result: 89336a85bf6d1e83eb20fbc92170705ded9b42285b30178ed8e855d65c4c4b69" << std::endl;
229229
if (!miningMode) {
230230
std::cout << "Performance: " << 1000 * elapsed / noncesCount << " ms per hash" << std::endl;
231231
}

‎src/vm_interpreted.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -434,12 +434,12 @@ namespace randomx {
434434
ibc.idst = &r[dst];
435435
if (dst != RegisterNeedsDisplacement) {
436436
ibc.isrc = &r[src];
437-
ibc.shift = instr.getModShift2();
437+
ibc.shift = instr.getModMem();
438438
ibc.imm = 0;
439439
}
440440
else {
441441
ibc.isrc = &r[src];
442-
ibc.shift = instr.getModShift2();
442+
ibc.shift = instr.getModMem();
443443
ibc.imm = signExtend2sCompl(instr.getImm32());
444444
}
445445
registerUsage[instr.dst] = i;
@@ -763,7 +763,7 @@ namespace randomx {
763763
//jump condition
764764
int reg = getConditionRegister(registerUsage);
765765
ibc.target = registerUsage[reg];
766-
ibc.shift = instr.getModShift3();
766+
ibc.shift = instr.getModShift();
767767
ibc.creg = &r[reg];
768768
for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
769769
registerUsage[j] = i;

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