COND_R instruction reworked as CBRANCH

instruction mod field bits reallocated

Author: tevador

doc/program.asm

@@ -44,14 +44,12 @@ namespace randomx {
 	static const char* regScratchpadAddr = "rsi";
 
 	void AssemblyGeneratorX86::generateProgram(Program& prog) {
-		for (unsigned i = 0; i < 8; ++i) {
+		for (unsigned i = 0; i < RegistersCount; ++i) {
 			registerUsage[i] = -1;
 		}
 		asmCode.str(std::string()); //clear
 		for (unsigned i = 0; i < prog.getSize(); ++i) {
-#if RANDOMX_JUMP
 			asmCode << "randomx_isn_" << i << ":" << std::endl;
-#endif
 			Instruction& instr = prog(i);
 			instr.src %= RegistersCount;
 			instr.dst %= RegistersCount;
@@ -261,7 +259,7 @@ namespace randomx {
 	void AssemblyGeneratorX86::genAddressRegDst(Instruction& instr, int maskAlign = 8) {
 		asmCode << "\tlea eax, [" << regR32[instr.dst] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
 		int mask;
-		if (instr.getModCond()) {
+		if (instr.getModCond() < StoreL3Condition) {
 			mask = instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask;
 		}
 		else {
@@ -277,9 +275,9 @@ namespace randomx {
 	void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) {
 		registerUsage[instr.dst] = i;
 		if(instr.dst == RegisterNeedsDisplacement)
-			asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
+			asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl;
 		else
-			asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModMem())) << "]" << std::endl;
+			asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << "]" << std::endl;
 		traceint(instr);
 	}
 
@@ -542,55 +540,18 @@ namespace randomx {
 		tracenop(instr);
 	}
 
-	static inline const char* condition(Instruction& instr) {
-		switch (instr.getModCond())
-		{
-			case 0:
-				return "be";
-			case 1:
-				return "a";
-			case 2:
-				return "s";
-			case 3:
-				return "ns";
-			case 4:
-				return "o";
-			case 5:
-				return "no";
-			case 6:
-				return "l";
-			case 7:
-				return "ge";
-			default:
-				UNREACHABLE;
-		}
-	}
-
-	void AssemblyGeneratorX86::handleCondition(Instruction& instr, int i) {
-		const int shift = instr.getModShift();
-		const int conditionMask = ((1 << RANDOMX_JUMP_BITS) - 1) << shift;
+	void AssemblyGeneratorX86::h_CBRANCH(Instruction& instr, int i) {
 		int reg = getConditionRegister();
 		int target = registerUsage[reg] + 1;
-		registerUsage[reg] = i;
-		asmCode << "\tadd " << regR[reg] << ", " << (1 << shift) << std::endl;
-		asmCode << "\ttest " << regR[reg] << ", " << conditionMask << std::endl;
+		int shift = instr.getModCond();
+		asmCode << "\tadd " << regR[reg] << ", " << (int32_t)(instr.getImm32() | (1 << shift)) << std::endl;
+		asmCode << "\ttest " << regR[reg] << ", " << (ConditionMask << shift) << std::endl;
 		asmCode << "\tjz randomx_isn_" << target << std::endl;
-		for (unsigned j = 0; j < 8; ++j) { //mark all registers as used
+		for (unsigned j = 0; j < RegistersCount; ++j) { //mark all registers as used
 			registerUsage[j] = i;
 		}
 	}
 
-	void AssemblyGeneratorX86::h_COND_R(Instruction& instr, int i) {
-#if RANDOMX_JUMP
-		handleCondition(instr, i);
-#endif
-		asmCode << "\txor ecx, ecx" << std::endl;
-		asmCode << "\tcmp " << regR32[instr.src] << ", " << (int32_t)instr.getImm32() << std::endl;
-		asmCode << "\tset" << condition(instr) << " cl" << std::endl;
-		asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
-		traceint(instr);
-	}
-
 	void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
 		genAddressRegDst(instr);
 		asmCode << "\tmov qword ptr [" << regScratchpadAddr << "+rax], " << regR[instr.src] << std::endl;
@@ -632,7 +593,7 @@ namespace randomx {
 		INST_HANDLE(FMUL_R)
 		INST_HANDLE(FDIV_M)
 		INST_HANDLE(FSQRT_R)
-		INST_HANDLE(COND_R)
+		INST_HANDLE(CBRANCH)
 		INST_HANDLE(CFROUND)
 		INST_HANDLE(ISTORE)
 		INST_HANDLE(NOP)

src/assembly_generator_x86.cpp

@@ -44,7 +44,6 @@ namespace randomx {
 		void genAddressRegDst(Instruction&, int);
 		int32_t genAddressImm(Instruction&);
 		int getConditionRegister();
-		void handleCondition(Instruction&, int);
 		void generateCode(Instruction&, int);
 		void traceint(Instruction&);
 		void traceflt(Instruction&);
@@ -76,7 +75,7 @@ namespace randomx {
 		void h_FMUL_R(Instruction&, int);
 		void h_FDIV_M(Instruction&, int);
 		void h_FSQRT_R(Instruction&, int);
-		void h_COND_R(Instruction&, int);
+		void h_CBRANCH(Instruction&, int);
 		void h_CFROUND(Instruction&, int);
 		void h_ISTORE(Instruction&, int);
 		void h_NOP(Instruction&, int);

src/assembly_generator_x86.hpp

@@ -40,13 +40,14 @@ namespace randomx {
 	static_assert(RANDOMX_SCRATCHPAD_L2 >= RANDOMX_SCRATCHPAD_L1, "RANDOMX_SCRATCHPAD_L2 must be greater than or equal to RANDOMX_SCRATCHPAD_L1.");
 	static_assert((RANDOMX_SCRATCHPAD_L1 & (RANDOMX_SCRATCHPAD_L1 - 1)) == 0, "RANDOMX_SCRATCHPAD_L1 must be a power of 2.");
 	static_assert(RANDOMX_CACHE_ACCESSES > 1, "RANDOMX_CACHE_ACCESSES must be greater than 1");
+	static_assert(RANDOMX_JUMP_BITS >= 1 && RANDOMX_JUMP_BITS <= 16, "RANDOMX_JUMP_BITS must be an integer in the range 1-16.");
 
 	constexpr int wtSum = RANDOMX_FREQ_IADD_RS + RANDOMX_FREQ_IADD_M + RANDOMX_FREQ_ISUB_R + \
 		RANDOMX_FREQ_ISUB_M + RANDOMX_FREQ_IMUL_R + RANDOMX_FREQ_IMUL_M + RANDOMX_FREQ_IMULH_R + \
 		RANDOMX_FREQ_IMULH_M + RANDOMX_FREQ_ISMULH_R + RANDOMX_FREQ_ISMULH_M + RANDOMX_FREQ_IMUL_RCP + \
 		RANDOMX_FREQ_INEG_R + RANDOMX_FREQ_IXOR_R + RANDOMX_FREQ_IXOR_M + RANDOMX_FREQ_IROR_R + RANDOMX_FREQ_ISWAP_R + \
 		RANDOMX_FREQ_FSWAP_R + RANDOMX_FREQ_FADD_R + RANDOMX_FREQ_FADD_M + RANDOMX_FREQ_FSUB_R + RANDOMX_FREQ_FSUB_M + \
-		RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R + RANDOMX_FREQ_COND_R + \
+		RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R + RANDOMX_FREQ_CBRANCH + \
 		RANDOMX_FREQ_CFROUND + RANDOMX_FREQ_ISTORE + RANDOMX_FREQ_NOP;
 
 	static_assert(wtSum == 256,	"Sum of instruction frequencies must be 256.");
@@ -59,6 +60,8 @@ namespace randomx {
 	constexpr uint32_t CacheSize = RANDOMX_ARGON_MEMORY * ArgonBlockSize;
 	constexpr uint64_t DatasetSize = RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE;
 	constexpr uint32_t DatasetExtraItems = RANDOMX_DATASET_EXTRA_SIZE / RANDOMX_DATASET_ITEM_SIZE;
+	constexpr uint32_t ConditionMask = ((1 << RANDOMX_JUMP_BITS) - 1);
+	constexpr int StoreL3Condition = 14;
 
 #ifdef TRACE
 	constexpr bool trace = true;
@@ -76,8 +79,6 @@ namespace randomx {
 #endif
 #endif
 
-#define RANDOMX_JUMP (RANDOMX_JUMP_BITS > 0)
-
 	using addr_t = uint32_t;
 
 	using int_reg_t = uint64_t;

src/common.hpp

@@ -64,7 +64,7 @@ along with RandomX.  If not, see<http://www.gnu.org/licenses/>.
 //Scratchpad L1 size in bytes. Must be a power of two and less than or equal to RANDOMX_SCRATCHPAD_L2.
 #define RANDOMX_SCRATCHPAD_L1      (16 * 1024)
 
-//How many register bits must be zero for a jump condition to be triggered. If set to 0, jumps are disabled.
+//How many register bits must be zero for CBRANCH instruction to jump. Must be an integer in the range 1-16.
 #define RANDOMX_JUMP_BITS          7
 
 /*
@@ -100,8 +100,9 @@ Total sum of frequencies must be 256
 #define RANDOMX_FREQ_FDIV_M         4
 #define RANDOMX_FREQ_FSQRT_R        6
 
-#define RANDOMX_FREQ_COND_R         8
+#define RANDOMX_FREQ_CBRANCH        8
 #define RANDOMX_FREQ_CFROUND        1
+
 #define RANDOMX_FREQ_ISTORE        16
 
 #define RANDOMX_FREQ_NOP            0

src/configuration.h

@@ -33,7 +33,7 @@ namespace randomx {
 	}
 
 	void Instruction::genAddressRegDst(std::ostream& os) const {
-		if (getModCond())
+		if (getModCond() < StoreL3Condition)
 			os << (getModMem() ? "L1" : "L2");
 		else
 			os << "L3";
@@ -49,7 +49,7 @@ namespace randomx {
 		if(dst == RegisterNeedsDisplacement) {
 			os << ", " << (int32_t)getImm32();
 		}
-		os << ", LSH " << (int)getModMem() << std::endl;
+		os << ", SHFT " << (int)getModShift() << std::endl;
 	}
 
 	void Instruction::h_IADD_M(std::ostream& os) const {
@@ -278,8 +278,8 @@ namespace randomx {
 		}
 	}
 
-	void Instruction::h_COND_R(std::ostream& os) const {
-		os << "r" << (int)dst << ", " << condition(getModCond()) << "(r" << (int)src << ", " << (int32_t)getImm32() << "), LSH " << (int)(getModShift()) << std::endl;
+	void Instruction::h_CBRANCH(std::ostream& os) const {
+		os << (int32_t)getImm32() << ", COND " << (int)(getModCond()) << std::endl;
 	}
 
 	void  Instruction::h_ISTORE(std::ostream& os) const {
@@ -321,7 +321,7 @@ namespace randomx {
 		INST_NAME(FMUL_R)
 		INST_NAME(FDIV_M)
 		INST_NAME(FSQRT_R)
-		INST_NAME(COND_R)
+		INST_NAME(CBRANCH)
 		INST_NAME(CFROUND)
 		INST_NAME(ISTORE)
 		INST_NAME(NOP)
@@ -354,7 +354,7 @@ namespace randomx {
 		INST_HANDLE(FMUL_R)
 		INST_HANDLE(FDIV_M)
 		INST_HANDLE(FSQRT_R)
-		INST_HANDLE(COND_R)
+		INST_HANDLE(CBRANCH)
 		INST_HANDLE(CFROUND)
 		INST_HANDLE(ISTORE)
 		INST_HANDLE(NOP)

src/instruction.cpp

@@ -57,7 +57,7 @@ namespace randomx {
 		constexpr int FMUL_R = 23;
 		constexpr int FDIV_M = 24;
 		constexpr int FSQRT_R = 25;
-		constexpr int COND_R = 26;
+		constexpr int CBRANCH = 26;
 		constexpr int CFROUND = 27;
 		constexpr int ISTORE = 28;
 		constexpr int NOP = 29;
@@ -81,11 +81,11 @@ namespace randomx {
 		int getModMem() const {
 			return mod % 4; //bits 0-1
 		}
-		int getModCond() const {
-			return (mod >> 2) % 8; //bits 2-4
-		}
 		int getModShift() const {
-			return mod >> 5; //bits 5-7
+			return (mod >> 2) % 4; //bits 2-3
+		}
+		int getModCond() const {
+			return mod >> 4; //bits 4-7
 		}
 		void setMod(uint8_t val) {
 			mod = val;
@@ -129,7 +129,7 @@ namespace randomx {
 		void h_FMUL_R(std::ostream&) const;
 		void h_FDIV_M(std::ostream&) const;
 		void h_FSQRT_R(std::ostream&) const;
-		void h_COND_R(std::ostream&) const;
+		void h_CBRANCH(std::ostream&) const;
 		void h_CFROUND(std::ostream&) const;
 		void h_ISTORE(std::ostream&) const;
 		void h_NOP(std::ostream&) const;