tests: lib: shared_multi_heap: fix ARM64 MMU attributes

The qemu_cortex_a53 overlay was using ARM MPU memory attributes
(DT_MEM_ARM(ATTR_MPU_RAM)) even though Cortex-A53 is an ARM64
platform with MMU, not MPU.

Fix by switching the overlay to DT_MEM_ARM64_MMU_NORMAL /
DT_MEM_ARM64_MMU_NORMAL_NC and updating the test source to
handle both ARM MPU and ARM64 MMU attributes via
#if defined(CONFIG_ARM64).

The ARM64 path now checks the generic DT_MEM_CACHEABLE bit
instead of switching on architecture-specific enum values,
consistent with the composable-bitmask design.

Use the generic DT_MEM_ARCH_ATTR_UNKNOWN for the "unknown
attribute" default instead of architecture-specific aliases.

Remove the runtime smh_reg_map() function and its call site
since memory regions are now statically mapped at compile time
via MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY_FROM_DT, making
the dynamic k_mem_map_phys_bare() mapping redundant.

Increase CONFIG_MAX_XLAT_TABLES to 16 for qemu_cortex_a53.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>

Author: kedareswararao

tests/lib/shared_multi_heap/boards/qemu_cortex_a53.conf

@@ -1,2 +1,3 @@
 CONFIG_HAVE_CUSTOM_LINKER_SCRIPT=y
 CONFIG_CUSTOM_LINKER_SCRIPT="linker_arm64_shared_pool.ld"
+CONFIG_MAX_XLAT_TABLES=16

tests/lib/shared_multi_heap/boards/qemu_cortex_a53.overlay

@@ -5,22 +5,22 @@
  */
 
 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
-#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm64.h>
 
 / {
 	soc {
 		res0: memory@42000000 {
 			compatible = "zephyr,memory-region", "mmio-sram";
 			reg = <0x0 0x42000000 0x0 0x1000>;
 			zephyr,memory-region = "RES0";
-			zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
+			zephyr,memory-attr = <DT_MEM_ARM64_MMU_NORMAL>;
 		};
 
 		res1: memory@43000000 {
 			compatible = "zephyr,memory-region", "mmio-sram";
 			reg = <0x0 0x43000000 0x0 0x2000>;
 			zephyr,memory-region = "RES1";
-			zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
+			zephyr,memory-attr = <DT_MEM_ARM64_MMU_NORMAL_NC>;
 		};
 
 		res_no_mpu: memory@45000000 {
@@ -33,7 +33,7 @@
 			compatible = "zephyr,memory-region", "mmio-sram";
 			reg = <0x0 0x44000000 0x0 0x3000>;
 			zephyr,memory-region = "RES2";
-			zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
+			zephyr,memory-attr = <DT_MEM_ARM64_MMU_NORMAL>;
 		};
 	};
 };

tests/lib/shared_multi_heap/src/main.c

@@ -7,13 +7,18 @@
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
 #include <zephyr/linker/linker-defs.h>
-#include <zephyr/kernel/mm.h>
+#if defined(CONFIG_ARM64)
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm64.h>
+#else
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#endif
 
 #include <zephyr/multi_heap/shared_multi_heap.h>
 
 #define DT_DRV_COMPAT		zephyr_memory_region
 
+#define SMH_DT_MEM_UNKNOWN_DEFAULT DT_MEM_ARCH_ATTR_UNKNOWN
+
 #define RES0_CACHE_ADDR		DT_REG_ADDR(DT_NODELABEL(res0))
 #define RES1_NOCACHE_ADDR	DT_REG_ADDR(DT_NODELABEL(res1))
 #define RES2_CACHE_ADDR		DT_REG_ADDR(DT_NODELABEL(res2))
@@ -29,29 +34,14 @@ struct region_map {
 			.addr = (uintptr_t) DT_INST_REG_ADDR(n),		\
 			.size = DT_INST_REG_SIZE(n),				\
 			.attr = DT_INST_PROP_OR(n, zephyr_memory_attr,		\
-						DT_MEM_ARM_MPU_UNKNOWN),	\
+						SMH_DT_MEM_UNKNOWN_DEFAULT),	\
 		},								\
 	},
 
 struct region_map map[] = {
 	DT_INST_FOREACH_STATUS_OKAY(FOREACH_REG)
 };
 
-#if defined(CONFIG_MMU)
-static void smh_reg_map(struct shared_multi_heap_region *region)
-{
-	uint32_t mem_attr;
-	uint8_t *v_addr;
-
-	mem_attr = (region->attr == SMH_REG_ATTR_CACHEABLE) ? K_MEM_CACHE_WB : K_MEM_CACHE_NONE;
-	mem_attr |= K_MEM_PERM_RW;
-
-	k_mem_map_phys_bare(&v_addr, region->addr, region->size, mem_attr);
-
-	region->addr = (uintptr_t) v_addr;
-}
-#endif /* CONFIG_MMU */
-
 /*
  * Given a virtual address retrieve the original memory region that the mapping
  * is belonging to.
@@ -67,34 +57,25 @@ static struct region_map *get_region_map(void *v_addr)
 	return NULL;
 }
 
-static inline enum shared_multi_heap_attr mpu_to_reg_attr(uint32_t dt_attr)
+static inline enum shared_multi_heap_attr dt_to_reg_attr(uint32_t dt_attr)
 {
-	/*
-	 * All the memory regions defined in the DT with the MPU property `RAM`
-	 * can be accessed and memory can be retrieved from using the attribute
-	 * `SMH_REG_ATTR_CACHEABLE`.
-	 *
-	 * All the memory regions defined in the DT with the MPU property
-	 * `RAM_NOCACHE` can be accessed and memory can be retrieved from using
-	 * the attribute `SMH_REG_ATTR_NON_CACHEABLE`.
-	 *
-	 * [MPU attr]   -> [SMH attr]
-	 *
-	 * RAM          -> SMH_REG_ATTR_CACHEABLE
-	 * RAM_NOCACHE  -> SMH_REG_ATTR_NON_CACHEABLE
-	 */
+#if defined(CONFIG_ARM64)
+	if (DT_MEM_ATTR_GET(dt_attr) & DT_MEM_CACHEABLE) {
+		return SMH_REG_ATTR_CACHEABLE;
+	}
+	return SMH_REG_ATTR_NON_CACHEABLE;
+#else
 	switch (DT_MEM_ARM_GET(dt_attr)) {
 	case DT_MEM_ARM_MPU_RAM:
 		return SMH_REG_ATTR_CACHEABLE;
 	case DT_MEM_ARM_MPU_RAM_NOCACHE:
 		return SMH_REG_ATTR_NON_CACHEABLE;
 	default:
-		/* How ? */
 		ztest_test_fail();
 	}
 
-	/* whatever */
 	return 0;
+#endif
 }
 
 static void fill_multi_heap(void)
@@ -105,28 +86,16 @@ static void fill_multi_heap(void)
 		reg_map = &map[idx];
 
 		/* zephyr,memory-attr property not found. Skip it. */
-		if (reg_map->region.attr == DT_MEM_ARM_MPU_UNKNOWN) {
+		if (reg_map->region.attr == SMH_DT_MEM_UNKNOWN_DEFAULT) {
 			continue;
 		}
 
 		/* Convert MPU attributes to shared-multi-heap capabilities */
-		reg_map->region.attr = mpu_to_reg_attr(reg_map->region.attr);
+		reg_map->region.attr = dt_to_reg_attr(reg_map->region.attr);
 
 		/* Assume for now that phys == virt */
 		reg_map->p_addr = reg_map->region.addr;
 
-#if defined(CONFIG_MMU)
-		/*
-		 * For MMU-enabled platform we have to MMU-map the physical
-		 * address retrieved by DT at run-time because the SMH
-		 * framework expects virtual addresses.
-		 *
-		 * For MPU-enabled platform the code is assuming that the
-		 * region are configured at build-time, so no map is needed.
-		 */
-		smh_reg_map(&reg_map->region);
-#endif /* CONFIG_MMU */
-
 		shared_multi_heap_add(&reg_map->region, NULL);
 	}
 }