bfd, gas, binutils: add support for the Xarcvudsp extension

This commit implements support for the ARC-V micro-DSP extension version
1.4, which is a 32-bit DSP-style extension mostly operating on 16-bit
data.  The assembly mnemonics resemble RVV instructions, but SEW and
LMUL are embedded in the instruction encoding instead of coming from a
CSR.  Since it reuses reserved RVV encodings, it is a non-conforming
extension.

TODO: add more text and pointers to public documentation.

Signed-off-by: Artemiy Volkov <[email protected]>

Author: artemiy-volkov

bfd/elfxx-riscv.c

@@ -1511,6 +1511,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xsfvcp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xsfcease",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xarcvudsp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2121,6 +2122,14 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
 	(_("`xtheadvector' is conflict with the `v' extension"));
       no_conflict = false;
     }
+  if (riscv_lookup_subset (rps->subset_list, "xarcvudsp", &subset)
+      && riscv_lookup_subset (rps->subset_list, "v", &subset))
+    {
+      rps->error_handler
+	(_("`xarcvudsp' is conflict with the `v' extension"));
+      no_conflict = false;
+    }
+
 
   bool support_zve = false;
   bool support_zvl = false;
@@ -2786,6 +2795,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xsfvcp");
     case INSN_CLASS_XSFCEASE:
       return riscv_subset_supports (rps, "xsfcease");
+    case INSN_CLASS_XARCVUDSP:
+      return riscv_subset_supports (rps, "xarcvudsp");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
@@ -3058,6 +3069,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadzvamo";
     case INSN_CLASS_XSFCEASE:
       return "xsfcease";
+    case INSN_CLASS_XARCVUDSP:
+      return "xarcvudsp";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));

gas/config/tc-riscv.c

@@ -1717,6 +1717,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		    goto unknown_validate_operand;
 		}
 		break;
+	    case 'a': /* Vendor-specific (ARC-V) operands.  */
+	      switch (*++oparg)
+		{
+		  case 'v': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
+		  default:
+		    goto unknown_validate_operand;
+		}
+		break;
 	    default:
 	      goto unknown_validate_operand;
 	    }
@@ -2685,6 +2693,97 @@ my_getThVsetvliExpression (expressionS *ep, char *str)
     }
 }
 
+static struct arcv_udsp_insn_vtype_combination {
+  const char *insn;
+  int sew;
+  int lmul;
+} arcv_udsp_insn_vtype_combinations[] = {
+  { "arcv.xvadd.vv", 0x1, 0 },
+  { "arcv.xvsub.vv", 0x1, 0 },
+  { "arcv.xvsadd.vv", 0x1, 0 },
+  { "arcv.xvsadd.vv", 0x2, 0 },
+  { "arcv.xvssub.vv", 0x1, 0 },
+  { "arcv.xvssub.vv", 0x2, 0 },
+  { "arcv.xvsll.vx", 0x1, 0 },
+  { "arcv.xvsra.vx", 0x1, 0 },
+  { "arcv.xvnclip.wx", 0x1, 0 },
+  { "arcv.xvnclip.wx", 0x1, 0x7 },
+  { "arcv.xvwmul.vv", 0x1, 0 },
+  { "arcv.xvwmul.vv", 0x1, 0x7 },
+  { "arcv.xvwsrdot.vv", 0x1, 0 },
+  { "arcv.xvscmul.vv", 0x1, 0 },
+  { "arcv.xvscjmul.vv", 0x1, 0 },
+  { "arcv.xvwscmul.vv", 0x1, 0 },
+  { "arcv.xvwscjmul.vv", 0x1, 0 },
+  { "arcv.xvwscrdot.vv", 0x1, 0 },
+  { "arcv.xvwscjrdot.vv", 0x1, 0 },
+  { 0 },
+};
+
+static bool
+arcv_udsp_opcode_supports_sew_lmul (char *insn, int sew, int lmul)
+{
+  for (struct arcv_udsp_insn_vtype_combination *ivc =
+				arcv_udsp_insn_vtype_combinations;
+       ivc->insn;
+       ivc++)
+    if (!strcmp (ivc->insn, insn) && ivc->sew == sew && ivc->lmul == lmul)
+      return true;
+
+  as_bad (_("bad ARC-V UDSP instruction: "
+    "combination of SEW and LMUL not supported for opcode"));
+
+  return false;
+}
+
+/* Parse string STR as a set of "vtype" operands of an ARC-V UDSP instruction
+   (the format is "eXX, mf?X"). Check legality of operands depending on the
+   instruction. Store the expression in *EP.
+   On exit, EXPR_PARSE_END points to the first character after the
+   expression.  */
+
+static void
+my_getArcvVtypeExpression (expressionS *ep, char *str, char *insn)
+{
+  unsigned int sew = 0, lmul = 0;
+  bfd_boolean vsew_found = FALSE, vlmul_found = FALSE;
+
+  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew),
+		  &sew))
+    {
+      if (*str == ',')
+	++str;
+      vsew_found = TRUE;
+    }
+  else as_bad (_("bad ARC-V UDSP instruction: SEW not specified"));
+
+  if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &lmul))
+    {
+      if (*str == ',')
+	++str;
+      vlmul_found = TRUE;
+    }
+  else as_bad (_("bad ARC-V UDSP instruction: LMUL not specified"));
+
+  if (!vsew_found || !vlmul_found
+      || !arcv_udsp_opcode_supports_sew_lmul (insn, sew, lmul))
+    {
+      my_getExpression (ep, str);
+      str = expr_parse_end;
+    }
+  else
+    {
+      gas_assert ((sew == 0x2 && lmul == 0)
+		  || (sew == 0x1 && (lmul == 0 || lmul == 0x7)));
+
+      ep->X_op = O_constant;
+      ep->X_add_number = (sew == 0x2 ? 0x4 :
+			  (lmul == 0 ? 0x2 : 0x1));
+      expr_parse_end = str;
+    }
+}
+
+
 /* Detect and handle implicitly zero load-store offsets.  For example,
    "lw t0, (t1)" is shorthand for "lw t0, 0(t1)".  Return true if such
    an implicit offset was detected.  */
@@ -4070,6 +4169,21 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 #undef ENCODE_UIMM_BIT_FIELD
 		  break;
 
+		case 'a': /* Vendor-specific (ARC-V) operands.  */
+		  switch (*++oparg)
+		    {
+		      case 'v':
+			my_getArcvVtypeExpression (imm_expr, asarg, insn->name);
+			asarg = expr_parse_end;
+			ip->insn_opcode
+			    |= (imm_expr->X_add_number & OP_MASK_FUNCT3)
+				<< OP_SH_FUNCT3;
+			  continue;
+		      default:
+			goto unknown_riscv_ip_operand;
+		    }
+		  break;
+
 		default:
 		  goto unknown_riscv_ip_operand;
 		}

gas/testsuite/gas/riscv/x-arcv-udsp-fail.d

@@ -0,0 +1,2 @@
+#as: -march=rv32i_xarcvudsp -I$srcdir/$subdir/
+#error_output: x-arcv-udsp-fail.l