arc64: Enable extra vector tests

Signed-off-by: Claudiu Zissulescu <[email protected]>

Author: claziss

gcc/testsuite/lib/target-supports.exp

@@ -4087,7 +4087,8 @@ proc check_effective_target_vect_int { } {
 	 || [is-effective-target arm_neon]
 	 || ([istarget mips*-*-*]
 	     && ([et-is-effective-target mips_loongson_mmi]
-	     || [et-is-effective-target mips_msa]))
+		 || [et-is-effective-target mips_msa]))
+	 || ([istarget arc64-*-])
 	 || ([istarget s390*-*-*]
 	     && [check_effective_target_s390_vx])
 	 || ([istarget riscv*-*-*]
@@ -4156,6 +4157,7 @@ proc check_effective_target_vect_complex_add_byte { } {
 	  && [check_effective_target_aarch64_little_endian])
 	 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
 	     && [check_effective_target_arm_little_endian])
+	 || ([istarget arc64-*-*])
 	}}]
 }
 
@@ -4171,6 +4173,7 @@ proc check_effective_target_vect_complex_add_short { } {
 	  && [check_effective_target_aarch64_little_endian])
 	 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
 	     && [check_effective_target_arm_little_endian])
+	 || ([istarget arc64-*-*])
 	}}]
 }
 
@@ -4219,6 +4222,7 @@ proc check_effective_target_vect_complex_add_half { } {
 	      && [check_effective_target_aarch64_little_endian])
 	 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
 	     && [check_effective_target_arm_little_endian])
+	 || ([check_effective_target_arc64_fp16_vfloat])
 	}}]
 }
 
@@ -4237,6 +4241,7 @@ proc check_effective_target_vect_complex_add_float { } {
 	      && [check_effective_target_aarch64_little_endian])
 	 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
 	     && [check_effective_target_arm_little_endian])
+	 || ([check_effective_target_arc64_fp32_vfloat])
 	}}]
 }
 
@@ -4252,6 +4257,7 @@ proc check_effective_target_vect_complex_add_double { } {
 	  && [check_effective_target_aarch64_little_endian])
 	 || ([check_effective_target_aarch64_sve2]
 	      && [check_effective_target_aarch64_little_endian]))
+	 || ([check_effective_target_arc64_fp64_vfloat])
 	}}]
 }
 
@@ -4544,6 +4550,40 @@ proc check_effective_target_arc64_atomic { } {
     }]
 }
 
+proc check_effective_target_arc64_fp16_vfloat { } {
+    if { ![istarget arc64-*-*] } {
+	return 0;
+    }
+    return [check_no_compiler_messages arc_fp16_vfloat assembly {
+	#if !defined(__ARC_FPU_SP__)
+	#error NO_16b_FLOATS
+	#endif
+    }]
+}
+
+proc check_effective_target_arc64_fp32_vfloat { } {
+    if { ![istarget arc64-*-*] } {
+	return 0;
+    }
+    return [check_no_compiler_messages arc_fp32_vfloat assembly {
+	#if !defined(__ARC_FPU_SP__)
+	#error NO_32b_FLOATS
+	#endif
+    }]
+}
+
+proc check_effective_target_arc64_fp64_vfloat { } {
+    if { ![istarget arc64-*-*] } {
+	return 0;
+    }
+    return [check_no_compiler_messages arc_fp64_vfloat assembly {
+	#if !defined(__ARC_FPU_DP__) && !defined(__ARC64_WIDE_VECTOR)
+	#error NO_64b_FLOATS
+	#endif
+    }]
+}
+
+
 # Return 1 if this is an arm target using 32-bit instructions
 proc check_effective_target_arm32 { } {
     if { ![istarget arm*-*-*] } {
@@ -7767,6 +7807,7 @@ proc check_effective_target_vect_perm { } {
 		     || [et-is-effective-target mips_msa]))
 	     || ([istarget s390*-*-*]
 		 && [check_effective_target_s390_vx])
+	     || ([istarget arc64-*-*])
 	     || [istarget amdgcn-*-*]
 	     || ([istarget riscv*-*-*]
 		 && [check_effective_target_riscv_v])
@@ -11773,6 +11814,9 @@ proc check_vect_support_and_set_flags { } {
       } else {
 	  set dg-do-what-default compile
       }
+    } elseif [istarget arc64-*-*] {
+	lappend DEFAULT_VECTCFLAGS "-ffast-math"
+	set dg-do-what-default run
     } else {
         return 0
     }