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13 | 13 |
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14 | 14 | (define_code_iterator arith_pattern1 [and plus ior xor minus ashift ashiftrt lshiftrt] )
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15 | 15 |
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16 |
| -(define_insn "*<arc64_code_map>_insn" |
| 16 | +(define_insn "*<arc64_code_map>_si_insn" |
17 | 17 | [(set ( match_operand:SI 0 "register_operand" "=q,r, r, r, r,r, r, r")
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18 |
| - (arith_pattern1:SI (match_operand:SI 1 "nonmemory_operand" "%0,0, 0, 0, r,r,ULIMM, r") |
| 18 | + (arith_pattern1:SI (match_operand:SI 1 "nonmemory_operand" " 0,0, 0, 0, r,r,ULIMM, r") |
19 | 19 | (match_operand:SI 2 "nonmemory_operand" " q,r,U06S0,S12S0,U06S0,r, r,ULIMM")))]
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20 | 20 | "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)"
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21 |
| - "<arc64_code_map>%?\\t%0,%1,%2" |
| 21 | + "<arc64_code_map>\\t%0,%1,%2" |
22 | 22 | [(set_attr "predicable" "no,yes,yes,no,no,no,no,no")
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23 | 23 | (set_attr "length" "2,4,4,4,4,4,8,8")
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24 | 24 | (set_attr "type" "<arc64_code_map>")]
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25 | 25 | )
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| 26 | + |
| 27 | +(define_insn "*<arc64_code_map>_di_insn" |
| 28 | + [(set ( match_operand:DI 0 "register_operand" "=r, r, r, r,r, r, r") |
| 29 | + (arith_pattern1:DI (match_operand:DI 1 "nonmemory_operand" " 0, 0, 0, r,r,ULIMM, r") |
| 30 | + (match_operand:DI 2 "nonmemory_operand" " r,U06S0,S12S0,U06S0,r, r,ULIMM")))] |
| 31 | + "register_operand (operands[1], DImode) || register_operand (operands[2], DImode)" |
| 32 | + "<arc64_code_map>l\\t%0,%1,%2" |
| 33 | + [(set_attr "predicable" "yes,yes,no,no,no,no,no") |
| 34 | + (set_attr "length" "4,4,4,4,4,8,8") |
| 35 | + (set_attr "type" "<arc64_code_map>")] |
| 36 | +) |
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