AArch64: fix aarch64_usubw pattern

It looks like during my pre-commit testrun I forgot to apply this patch
to the patch stack.  It had a typo in the element size.

It also looks like since the hi/lo operations take different element
counts for the assembler syntax that I can't have a unified pattern.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md
	(aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip,
	aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): Split into...
	(aarch64_uaddw<mode>_lo_zip, aarch64_uaddw<mode>_hi_zip,
	"aarch64_usubw<mode>_lo_zip, "aarch64_usubw<mode>_hi_zip): ... This.
	* config/aarch64/iterators.md (PERM_EXTEND, perm_index): Remove.
	(perm_hilo): Remove UNSPEC_ZIP1, UNSPEC_ZIP2.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/uxtl-combine-4.c: Fix typo.
	* gcc.target/aarch64/uxtl-combine-5.c: Likewise.
	* gcc.target/aarch64/uxtl-combine-6.c: Likewise.

Author: TamarChristinaArm

gcc/config/aarch64/aarch64-simd.md

@@ -4810,31 +4810,59 @@
   [(set_attr "type" "neon_sub_widen")]
 )
 
-(define_insn "aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip"
+(define_insn "aarch64_usubw<mode>_lo_zip"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
 	(minus:<VWIDE>
 	  (match_operand:<VWIDE> 1 "register_operand" "w")
 	  (subreg:<VWIDE>
 	    (unspec:<MODE> [
 		(match_operand:VQW 2 "register_operand" "w")
 		(match_operand:VQW 3 "aarch64_simd_imm_zero")
-	       ] PERM_EXTEND) 0)))]
+	       ] UNSPEC_ZIP1) 0)))]
   "TARGET_SIMD"
-  "usubw<PERM_EXTEND:perm_index>\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
+  "usubw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
   [(set_attr "type" "neon_sub_widen")]
 )
 
-(define_insn "aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip"
+(define_insn "aarch64_uaddw<mode>_lo_zip"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
 	(plus:<VWIDE>
 	  (subreg:<VWIDE>
 	    (unspec:<MODE> [
 		(match_operand:VQW 2 "register_operand" "w")
 		(match_operand:VQW 3 "aarch64_simd_imm_zero")
-	       ] PERM_EXTEND) 0)
+	       ] UNSPEC_ZIP1) 0)
 	  (match_operand:<VWIDE> 1 "register_operand" "w")))]
   "TARGET_SIMD"
-  "uaddw<PERM_EXTEND:perm_index>\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
+  "uaddw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
+  [(set_attr "type" "neon_add_widen")]
+)
+
+(define_insn "aarch64_usubw<mode>_hi_zip"
+  [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+	(minus:<VWIDE>
+	  (match_operand:<VWIDE> 1 "register_operand" "w")
+	  (subreg:<VWIDE>
+	    (unspec:<MODE> [
+		(match_operand:VQW 2 "register_operand" "w")
+		(match_operand:VQW 3 "aarch64_simd_imm_zero")
+	       ] UNSPEC_ZIP2) 0)))]
+  "TARGET_SIMD"
+  "usubw2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
+  [(set_attr "type" "neon_sub_widen")]
+)
+
+(define_insn "aarch64_uaddw<mode>_hi_zip"
+  [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+	(plus:<VWIDE>
+	  (subreg:<VWIDE>
+	    (unspec:<MODE> [
+		(match_operand:VQW 2 "register_operand" "w")
+		(match_operand:VQW 3 "aarch64_simd_imm_zero")
+	       ] UNSPEC_ZIP2) 0)
+	  (match_operand:<VWIDE> 1 "register_operand" "w")))]
+  "TARGET_SIMD"
+  "uaddw2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
   [(set_attr "type" "neon_add_widen")]
 )
 

gcc/config/aarch64/iterators.md

@@ -2645,9 +2645,6 @@
 (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
 				    UNSPEC_UZP1 UNSPEC_UZP2])
 
-;; Permutes for zero extends
-(define_int_iterator PERM_EXTEND [UNSPEC_ZIP1 UNSPEC_ZIP2])
-
 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
 
 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
@@ -3470,10 +3467,7 @@
 			 (UNSPEC_REV16 "16")])
 
 (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
-			    (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")
-			    (UNSPEC_ZIP2 "hi") (UNSPEC_ZIP1 "lo")])
-
-(define_int_attr perm_index [(UNSPEC_ZIP2 "2") (UNSPEC_ZIP1 "")])
+			    (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
 
 ;; Return true if the associated optab refers to the high-numbered lanes,
 ;; false if it refers to the low-numbered lanes.  The convention is for

gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c

@@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n)
 /* { dg-final { scan-assembler-not {\tzip1\t} } } */
 /* { dg-final { scan-assembler-not {\tzip2\t} } } */
 /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */
-/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */
+/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */
 

gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c

@@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n)
 /* { dg-final { scan-assembler-not {\tzip1\t} } } */
 /* { dg-final { scan-assembler-not {\tzip2\t} } } */
 /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */
-/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */
+/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */
 

gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c

@@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n)
 /* { dg-final { scan-assembler-not {\tzip1\t} } } */
 /* { dg-final { scan-assembler-not {\tzip2\t} } } */
 /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */
-/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */
+/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */