arc64: Use bclrl,bsetl and vpack to load large integers

Author: claziss

gcc/config/arc64/arc64.cc

@@ -1110,8 +1110,8 @@ arc64_legitimate_constant1_p (machine_mode mode, rtx x, bool nosym)
 {
   switch (GET_CODE (x))
     {
-    case CONST_DOUBLE:
     case CONST_INT:
+    case CONST_DOUBLE:
     case CONST_WIDE_INT:
     case HIGH:
       if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
@@ -1690,6 +1690,9 @@ arc64_get_effective_mode_for_address_scaling (const machine_mode mode)
      'C': Constant address, switches on/off @plt.
      's': Scalled immediate.
      'S': Scalled immediate, to be used in pair with 's'.
+     'T': Like 's' but the immediate is not limited to sub123 type insns.
+     't': Like 'T' but the input immediate is bitwise complemented.
+     'q': Sign extended lower 32bit of an immediate.
      'N': Negative immediate, to be used in pair with 's'.
      'V': 2x16b vector immediate, hi lane is zero.
      'P': Constant address, swithces on/off _s to be used with 'C'
@@ -1718,6 +1721,7 @@ arc64_print_operand (FILE *file, rtx x, int code)
 
   int scalled = 0;
   int sign = 1;
+  bool invert = false;
   machine_mode effective_mode;
 
   switch (code)
@@ -1809,7 +1813,7 @@ arc64_print_operand (FILE *file, rtx x, int code)
 	  return;
 	}
       ival = INTVAL (x);
-      ival &= 0xffffffffULL;
+      ival = zext_hwi (ival, 32);
       fprintf (file,"0x%08" PRIx32, (uint32_t) ival);
       break;
 
@@ -1899,6 +1903,36 @@ arc64_print_operand (FILE *file, rtx x, int code)
 	fputs ("_s", file);
       break;
 
+    case 't':
+      invert = true;
+      /* FALLTHRU */
+    case 'T':
+      if (!CONST_INT_P (x))
+	{
+	  output_operand_lossage ("invalid operand for %%s code");
+	  return;
+	}
+      ival = INTVAL (x);
+      if (invert)
+	  ival = ~ival;
+
+      ival = zext_hwi (ival >> 32, 32) << 32;
+      ival = ctz_hwi (ival);
+
+      asm_fprintf (file, "%d", (int) ival);
+      break;
+
+    case 'q':
+      if (!CONST_INT_P (x))
+	{
+	  output_operand_lossage ("invalid operand for %%s code");
+	  return;
+	}
+      ival = INTVAL (x);
+      ival = sext_hwi (ival, 32);
+      asm_fprintf (file, "%d", (int) ival);
+      break;
+
     case 's':
       if (REG_P (x))
 	break;
@@ -5042,7 +5076,7 @@ arc64_prepare_move_operands (rtx op0, rtx op1, machine_mode mode)
 	{
 	case CONST_INT:
 	  gcc_assert (mode == Pmode);
-	  if (!SIGNED_INT32 (INTVAL (op1)) && !UNSIGNED_INT32 (INTVAL (op1)))
+	  if (splittable_const_int_operand (op1, mode))
 	    {
 	      HOST_WIDE_INT val;
 	      /* We have a large 64bit immediate:

gcc/config/arc64/arc64.h

@@ -508,6 +508,10 @@ extern const enum reg_class arc64_regno_to_regclass[];
 
 #define  IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
 
+/* If this is a single bit mask, then we can load it with bset.  */
+#define SINGLE_BIT_MASK_OPERAND(VALUE)					\
+  (pow2p_hwi (VALUE))
+
 /* These assume that REGNO is a hard or pseudo reg number.
    They give nonzero only if REGNO is a hard reg of the suitable class
    or a pseudo reg currently allocated to a suitable hard reg.

gcc/config/arc64/arc64.md

@@ -969,8 +969,8 @@ xorl"
 ;; Long insns: movl, stl, ldl
 ;;
 (define_insn "*arc64_movdi"
-   [(set (match_operand:DI 0 "arc64_dest_operand" "=qh,    q,r,    r,         r,    r,Ucnst,    r,r,Ustk<,Ustor")
-	 (match_operand:DI 1 "arc64_movl_operand"  "qh,U08S0,r,S12S0,S32S0SymMV,SyPic,S32S0,Ustk>,m,    r, r"))]
+   [(set (match_operand:DI 0 "arc64_dest_operand" "=qh,    q,    r,    r,r,    r,         r,    r,    r,Ucnst,    r,r,Ustk<,Ustor")
+	 (match_operand:DI 1 "arc64_movl_operand"  "qh,U08S0,BCLRX,BSETX,r,S12S0,S32S0SymMV,U38S0,SyPic,S32S0,Ustk>,m,    r, r"))]
    "TARGET_64BIT
     && (register_operand (operands[0], DImode)
         || register_operand (operands[1], DImode)
@@ -979,17 +979,20 @@ xorl"
    "@
     movl_s\\t%0,%1
     movl_s\\t%0,%1
+    bclrl\\t%0,%q1,%t1
+    bsetl\\t%0,%L1,%T1
     movl\\t%0,%1
     movl\\t%0,%1
     movl\\t%0,%1
+    vpack2wl\\t%0,%L1,%H1
     addl\\t%0,pcl,%1
     stl%U0\\t%1,%0
     popl_s\\t%0
     ldl%U1\\t%0,%1
     pushl_s\\t%1
     stl%U0\\t%1,%0"
-   [(set_attr "type" "move,move,move,move,move,addl,st,ld,ld,st,st")
-    (set_attr "length" "2,2,4,4,8,8,8,2,*,2,*")]
+   [(set_attr "type" "move,move,bclr,bset,move,move,move,vpack,addl,st,ld,ld,st,st")
+    (set_attr "length" "2,2,8,8,4,4,8,8,8,8,2,*,2,*")]
 )
 
 ;; Hi/Low moves for constant and symbol loading.

gcc/config/arc64/constraints.md

@@ -383,6 +383,25 @@
     (match_code "const_int")
     (match_test "SIGNED_INT16 (ival)")))
 
+(define_constraint "BSETX" "@internal
+  A 1-bit + 32b integer constant suitable for BSET instruction"
+  (and
+    (match_code "const_int")
+    (match_test "SINGLE_BIT_MASK_OPERAND (zext_hwi (ival >> 32, 32))")
+    (match_test "UNSIGNED_INT32 (zext_hwi (ival, 32))")))
+
+(define_constraint "BCLRX" "@internal
+  A 1-bit + 32b integer constant suitable for BCLR instruction"
+  (and
+    (match_code "const_int")
+    (match_test "SINGLE_BIT_MASK_OPERAND (zext_hwi ((~ival) >> 32, 32))")
+    (match_test "(sext_hwi (ival, 32)) < 0")))
+
+(define_constraint "U38S0" "@internal
+  A 38-bit integer constant suitable for VPACK2WL instruction"
+  (and
+    (match_code "const_int")
+    (match_test "UNSIGNED (ival, 38)")))
 
 ; TODO: Below this line definition should be corrected
 (define_constraint "SR_R0"

gcc/config/arc64/predicates.md

@@ -18,6 +18,33 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
+;; A legitimate CONST_INT operand that takes more than one instruction
+;; to load
+(define_predicate "splittable_const_int_operand"
+  (match_code "const_int")
+{
+  /* ARC32 can fit all.  */
+  if (!TARGET_64BIT)
+    return false;
+
+  /* Check if we can fit it in a standard LIMM/XLIMM field.  */
+  if (SIGNED_INT32 (INTVAL (op)) || UNSIGNED_INT32 (INTVAL (op)))
+    return false;
+
+  /* Check if the constant can be loaded in a single bsetl/bclrl instruction.  */
+  if ((SINGLE_BIT_MASK_OPERAND (zext_hwi (INTVAL (op) >> 32, 32))
+       && UNSIGNED_INT32 (zext_hwi (INTVAL (op), 32)))
+      || (SINGLE_BIT_MASK_OPERAND (zext_hwi ((~INTVAL (op)) >> 32, 32))
+	  && (sext_hwi (INTVAL (op), 32) < 0)))
+    return false;
+
+  /* Check if the constant can be loaded in a single vpack2wl instruction.  */
+  if (UNSIGNED (INTVAL (op), 38))
+    return false;
+
+  return true;
+})
+
 ;; Place holder for mov operand predicate
 (define_predicate "arc64_movl_operand"
   (and (match_code "unspec,reg, subreg, mem, const, const_int, symbol_ref, label_ref")
@@ -30,8 +57,7 @@
 		 (ior (match_test "XINT (op,1) == ARC64_UNSPEC_PCREL")
 		      (match_test "XINT (op,1) == ARC64_UNSPEC_TLS_GD")))
 	    (and (match_code "const_int")
-		 (ior (match_test "UNSIGNED_INT32 (INTVAL (op))")
-		      (match_test "SIGNED_INT32 (INTVAL (op))"))))))
+		 (match_test "!splittable_const_int_operand (op, mode)")))))
 
 (define_predicate "arc64_movf_operand"
   (and (match_code "reg, subreg, mem, const, const_double")