[ARCx] movqi: Add w6 immediate store

Signed-off-by: Shahab Vahedi <[email protected]>

Author: Shahab Vahedi

gcc/config/arc64/arc64.h

@@ -366,6 +366,7 @@ extern const enum reg_class arc64_regno_to_regclass[];
 #define UNSIGNED_INT32(X) (UNSIGNED(X,32))
 
 #define SIGNED_INT3(X) (SIGNED(X,3))
+#define SIGNED_INT6(X) (SIGNED(X,6))
 #define SIGNED_INT7(X) (SIGNED(X,7))
 #define SIGNED_INT8(X) (SIGNED(X,8))
 #define SIGNED_INT9(X) (SIGNED(X,9))

gcc/config/arc64/arc64.md

@@ -266,14 +266,19 @@ unknown, xor, xorl"
 ;; stb_s          b   , [sp, u7]
 ;; stb_s          c   , [b , u5]
 (define_insn "*arc64_movqi"
-   [(set (match_operand:QI 0 "nonimmediate_operand" "=r, r, r, m")
-	 (match_operand:QI 1 "general_operand"      " r, i, m, r"))
+   [(set (match_operand:QI 0 "nonimmediate_operand" "=r, r,     m, r, m")
+	 (match_operand:QI 1 "general_operand"      " r, i, S06S0, m, r"))
    ]
+   ; in general, at least one of the operands must be a register
    "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
+   || register_operand (operands[1], QImode)
+   /* this is to match 'stb w6, [limm]' (S06S0 is the w6) */
+   || (satisfies_constraint_S06S0 (operands[1])
+       && memory_operand (operands[0], QImode))"
    "@
     mov\\t%0,%1
     mov\\t%0,%1
+    stb\\t%1,[%0]
     ldb\\t%0,[%1]
     stb\\t%1,[%0]"
 )

gcc/config/arc64/constraints.md

@@ -86,8 +86,14 @@
   (and (match_code "const_int")
        (match_test "UNSIGNED_INT6 (ival - 1)")))
 
-;---------------------------------------------------------
 
+(define_constraint "S06S0" "@internal
+  A 6-bit signed integer constant"
+  (and
+    (match_code "const_int")
+    (match_test "SIGNED_INT6 (ival)")))
+
+;---------------------------------------------------------
 
 (define_constraint "U06S0" "@internal
   A 6-bit unsigned integer constant"