ARC: [axs101] Fix HDMI frequency divider for v3 motherboard.

On v2 motherboard it was the only clock source for all purposes and for clocking
HDMI phy in particular. It was 25MHz. It lead to a fact that HDMI pixel clock
was 75MHz instead of 74.25MHz required by spec.

Even though on most monitors/TVs we still had normal picture there was a chance
in some corner-cases get problems with image display.

This problem was resolved on v3 motherboard with addition of another clock
source with 27MHz frequency.

Now to support both motherboard at once we check its version and do proper
divider setup.

Signed-off-by: Alexey Brodkin <[email protected]>
Signed-off-by: Paul Moers <[email protected]>

Author: abrodkin

arch/arc/plat-axs10x/axs101.c

@@ -178,18 +178,38 @@ static void axs101_early_init(void)
 	/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for rev 2 boards) */
 	iowrite32(0x52, (void __iomem *) AXC001_CREG + 0x114);
 
-	/*
-	 * Set clock for PGU, 150 Mhz
-	 * to obtain 75MHz pixel clock, required for 720p60
-	 * (25 * 18) / 3 == 25 * 6 == 150
-	 */
-
-	write_cgu_reg(0x2000,
-		      (void __iomem *) 0xe0010080, (void __iomem *) 0xe0010110);
-	write_cgu_reg((18 << 6) | 18,
-		      (void __iomem *) 0xe0010084, (void __iomem *) 0xe0010110);
-	write_cgu_reg((3 << 6) | 3,
-		      (void __iomem *) 0xe0010088, (void __iomem *) 0xe0010110);
+	/* Set clock divider value depending on mother board version */
+	if (ioread32((void __iomem *) AXS_MB_CREG + 0x234) & (1 << 28)) {
+		/*
+		 * 1 => HT-3 (rev3.0)
+		 *
+		 * Set clock for PGU, 74.25 Mhz
+		 * to obtain 74.25MHz pixel clock, required for 720p60
+		 * (27 * 22) / 8 == 74.25
+		 */
+		write_cgu_reg(0x2041, (void __iomem *) 0xe0010080,
+			      (void __iomem *) 0xe0010110);
+		write_cgu_reg((22 << 6) | 22, (void __iomem *) 0xe0010084,
+			      (void __iomem *) 0xe0010110);
+		write_cgu_reg((8 << 6) | 8, (void __iomem *) 0xe0010088,
+			      (void __iomem *) 0xe0010110);
+	}
+	else {
+		/*
+		 * 0 => HT-2 (rev2.0)
+		 *
+		 * Set clock for PGU, 150 Mhz
+		 * to obtain 75MHz pixel clock, required for 720p60
+		 * (25 * 18) / 3 == 25 * 6 == 150
+		 */
+
+		write_cgu_reg(0x2000, (void __iomem *) 0xe0010080,
+			      (void __iomem *) 0xe0010110);
+		write_cgu_reg((18 << 6) | 18, (void __iomem *) 0xe0010084,
+			      (void __iomem *) 0xe0010110);
+		write_cgu_reg((3 << 6) | 3, (void __iomem *) 0xe0010088,
+			      (void __iomem *) 0xe0010110);
+	}
 }
 
 static void axs101_plat_init(void)