From 6c31f3ea66561dd1d962cfba790547aec8ca3be3 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 14:28:10 +0800
Subject: [PATCH 01/22] Updated RCU peripheral

---
 devices/gd32f425.yaml       |   1 +
 peripherals/rcu/rcu_f4.yaml | 349 ++++++++++++++++++++++++++++++++++++
 2 files changed, 350 insertions(+)
 create mode 100644 peripherals/rcu/rcu_f4.yaml

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index c2bf2dd95..9bf1ed102 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -8,3 +8,4 @@ _modify:
   name: "GD32F425"
 _include:
   - common_patches/gd32f425.yaml
+  - ../peripherals/rcu/rcu_f4.yaml
diff --git a/peripherals/rcu/rcu_f4.yaml b/peripherals/rcu/rcu_f4.yaml
new file mode 100644
index 000000000..6555e3654
--- /dev/null
+++ b/peripherals/rcu/rcu_f4.yaml
@@ -0,0 +1,349 @@
+RCU:
+  CTL0:
+    "PLL*STB":
+      _read:
+        NotReady: [0, "PLL is not stable"]
+        Ready: [1, "PLL is stable"]
+    "PLL*EN":
+      "Off": [0, "Clock Off"]
+      "On": [1, "Clock On"]
+    CKMEN:
+      "Off": [0, "Clock monitor disabled"]
+      "On": [1, "Clock monitor enabled"]
+    HXTALBPS:
+      NotBypassed: [0, "HXTAL crystal oscillator not bypassed"]
+      Bypassed: [1, "HXTAL crystal oscillator bypassed with external clock"]
+    HXTALSTB:
+      _read:
+        NotReady: [0, "HXTAL is not stable"]
+        Ready: [1, "HXTAL is stable"]
+    HXTALEN:
+      "Off": [0, "Clock Off"]
+      "On": [1, "Clock On"]
+    IRC16MCALIB: [0, 255]
+    IRC16MADJ: [0, 31]
+    IRC16MSTB:
+      _read:
+        NotReady: [0, "IRC16M is not stable"]
+        Ready: [1, "IRC16M is stable"]
+    IRC16MEN:
+      "Off": [0, "Clock Off"]
+      "On": [1, "Clock On"]
+  PLL:
+    PLLQ:
+      DIV2: [2, "PLL divisor Q set to 2."]
+      DIV3: [3, "PLL divisor Q set to 3."]
+      DIV4: [4, "PLL divisor Q set to 4."]
+      DIV5: [5, "PLL divisor Q set to 5."]
+      DIV6: [6, "PLL divisor Q set to 6."]
+      DIV7: [7, "PLL divisor Q set to 7."]
+      DIV8: [8, "PLL divisor Q set to 8."]
+      DIV9: [9, "PLL divisor Q set to 9."]
+      DIV10: [10, "PLL divisor Q set to 10."]
+      DIV11: [11, "PLL divisor Q set to 11."]
+      DIV12: [12, "PLL divisor Q set to 12."]
+      DIV13: [13, "PLL divisor Q set to 13."]
+      DIV14: [14, "PLL divisor Q set to 14."]
+      DIV15: [15, "PLL divisor Q set to 15."]
+    PLLSEL:
+      IRC16M: [0, "IRC16M selected as the source clock of the PLL, PLLSAI, PLLI2S"]
+      HXTAL: [1, "HXTAL selected as the source clock of PLL, PLLSAI, PLLI2S"]
+    PLLP:
+      DIV2: [0, "PLL division factor P set to 2"]
+      DIV4: [1, "PLL division factor P set to 4"]
+      DIV8: [2, "PLL division factor P set to 8"]
+  CFG0:
+    CKOUT1SEL:
+      SYSCLK: [0, "System clock selected"]
+      PLLI2SR: [1, "PLL I2S clock selected"]
+      HXTAL: [2, "External high speed oscillator clock selected"]
+      PLLP: [3, "PLL clock selected"]
+    CKOUT1DIV:
+      DIV1: [0, "CK_OUT1 is divided by 1"]
+      DIV2: [4, "CK_OUT1 is divided by 2"]
+      DIV3: [5, "CK_OUT1 is divided by 3"]
+      DIV4: [6, "CK_OUT1 is divided by 4"]
+      DIV5: [7, "CK_OUT1 is divided by 5"]
+    CKOUT0DIV:
+      DIV1: [0, "CK_OUT0 is divided by 1"]
+      DIV2: [4, "CK_OUT0 is divided by 2"]
+      DIV3: [5, "CK_OUT0 is divided by 3"]
+      DIV4: [6, "CK_OUT0 is divided by 4"]
+      DIV5: [7, "CK_OUT0 is divided by 5"]
+    I2SSEL:
+      CK_PLLI2S: [0, "PLLI2S output clock selected as the I2S clock source."]
+      CK_I2S: [1, "External I2S_CKIN pin selected as I2S source clock."]
+    CKOUT0SEL:
+      IRC16M: [0, "Internal 16 MHz RC oscillator clock selected"]
+      LXTAL: [1, "External low speed oscillator clock selected"]
+      HXTAL: [2, "External high speed oscillator clock selected"]
+      CK_PLLP: [3, "PLL clock selected"]
+    RTCDIV:
+      NoClk: [0, "No clock selected for RTC"]
+      DIV2: [2, "CK_HXTAL is divided by 2"]
+      DIV3: [3, "CK_HXTAL is divided by 3"]
+      DIV4: [4, "CK_HXTAL is divided by 4"]
+      DIV5: [5, "CK_HXTAL is divided by 5"]
+      DIV6: [6, "CK_HXTAL is divided by 6"]
+      DIV7: [7, "CK_HXTAL is divided by 7"]
+      DIV8: [8, "CK_HXTAL is divided by 8"]
+      DIV9: [9, "CK_HXTAL is divided by 9"]
+      DIV10: [10, "CK_HXTAL is divided by 10"]
+      DIV11: [11, "CK_HXTAL is divided by 11"]
+      DIV12: [12, "CK_HXTAL is divided by 12"]
+      DIV13: [13, "CK_HXTAL is divided by 13"]
+      DIV14: [14, "CK_HXTAL is divided by 14"]
+      DIV15: [15, "CK_HXTAL is divided by 15"]
+      DIV16: [16, "CK_HXTAL is divided by 16"]
+      DIV17: [17, "CK_HXTAL is divided by 17"]
+      DIV18: [18, "CK_HXTAL is divided by 18"]
+      DIV19: [19, "CK_HXTAL is divided by 19"]
+      DIV20: [20, "CK_HXTAL is divided by 20"]
+      DIV21: [21, "CK_HXTAL is divided by 21"]
+      DIV22: [22, "CK_HXTAL is divided by 22"]
+      DIV23: [23, "CK_HXTAL is divided by 23"]
+      DIV24: [24, "CK_HXTAL is divided by 24"]
+      DIV25: [25, "CK_HXTAL is divided by 25"]
+      DIV26: [26, "CK_HXTAL is divided by 26"]
+      DIV27: [27, "CK_HXTAL is divided by 27"]
+      DIV28: [28, "CK_HXTAL is divided by 28"]
+      DIV29: [29, "CK_HXTAL is divided by 29"]
+      DIV30: [30, "CK_HXTAL is divided by 30"]
+      DIV31: [31, "CK_HXTAL is divided by 31"]
+    "APB[12]PSC":
+      DIV1: [0, "CK_AHB selected"]
+      DIV2: [4, "CK_AHB/2 selected"]
+      DIV4: [5, "CK_AHB/4 selected"]
+      DIV8: [6, "CK_AHB/8 selected"]
+      DIV16: [7, "CK_AHB/16 selected"]
+    AHBPSC:
+      Div1: [0, "CK_SYS"]
+      Div2: [8, "CK_SYS divided by 2"]
+      Div4: [9, "CK_SYS divided by 4"]
+      Div8: [10, "CK_SYS divided by 8"]
+      Div16: [11, "CK_SYS divided by 16"]
+      Div64: [12, "CK_SYS divided by 64"]
+      Div128: [13, "CK_SYS divided by 128"]
+      Div256: [14, "CK_SYS divided by 256"]
+      Div512: [15, "CK_SYS divided by 512"]
+    SCSS:
+      IRC16M: [0, "IRC16M selected as the system clock"]
+      HXTAL: [1, "HXTAL selected as the system clock."]
+      PPLLP: [2, "Select CK_PLLP as the system clock."]
+    SCS:
+      IRC16M: [0, "Select IRC16M as the system clock source."]
+      HXTAL: [1, "Select the HXTAL as the system clock source."]
+      PLLP: [2, "Select the PLLP as the system clock source."]
+  INT:
+    CKMIC:
+      _write:
+        Clear: [1, "Clear CKMIF flag"]
+    CKMIF:
+      _read:
+        NotInterrupted: [0, "Clock operating normally"]
+        Interrupted: [1, "HXTAL clock stuck"]
+    PLL*STBIC:
+      _write:
+        Clear: [1, "Clear PLLSTBIF flag"]
+    PLL*STBIE:
+      Disabled: [0, "Interrupt disabled"]
+      Enabled: [1, "Interrupt enabled"]
+    PLL*STBIF:
+      _read:
+        NotInterrupted: [0, "No interrupt generated"]
+        Interrupted: [1, "PLL stabilisation interrupt generated"]
+    HXTALSTBIE:
+      Disabled: [0, "Interrupt disabled"]
+      Enabled: [1, "Interrupt enabled"]
+    HXTALSTBIF:
+      _read:
+        NotInterrupted: [0, "No interrupt generated"]
+        Interrupted: [1, "HXTAL stabilisation interrupt generated"]
+    LXTALSTBIC:
+      _write:
+        Clear: [1, "Clear LXTALSTBIF flag"]
+    LXTALSTBIE:
+      Disabled: [0, "Interrupt disabled"]
+      Enabled: [1, "Interrupt enabled"]
+    LXTALSTBIF:
+      _read:
+        NotInterrupted: [0, "No interrupt generated"]
+        Interrupted: [1, "LXTAL stabilisation interrupt generated"]
+    IRC16MSTBIC:
+      _write:
+        Clear: [1, "Clear IRC16MSTBIF flag"]
+    IRC16MSTBIE:
+      Disabled: [0, "Interrupt disabled"]
+      Enabled: [1, "Interrupt enabled"]
+    IRC16MSTBIF:
+      _read:
+        NotInterrupted: [0, "No interrupt generated"]
+        Interrupted: [1, "IRC16M stabilisation interrupt generated"]
+    IRC32KSTBIC:
+      _write:
+        Clear: [1, "Clear IRC32KSTBIF flag"]
+    IRC32KSTBIE:
+      Disabled: [0, "Interrupt disabled"]
+      Enabled: [1, "Interrupt enabled"]
+    IRC32KSTBIF:
+      _read:
+        NotInterrupted: [0, "No interrupt generated"]
+        Interrupted: [1, "IRC32K stabilisation interrupt generated"]
+  "AHB[123]RST":
+    "*RST":
+      Reset: [1, "Reset the selected module."]
+  "AHB[123]EN":
+    "*EN":
+      Disable: [0, "Disable the selected module clock."]
+      Enable: [1, "Enable the selected module clock."]
+  "APB[12]RST":
+    "*RST":
+      Reset: [1, "Reset the selected module."]
+  "APB[12]EN":
+    "*EN":
+      Disable: [0, "Disable the selected module clock."]
+      Enable: [1, "Enable the selected module clock."]
+  "AHB[123]SPEN":
+    "*EN":
+      Disable: [0, "Disable the selected module in sleep mode."]
+      Enable: [1, "Enable the selected module in sleep mode."]
+  "APB[12]SPEN,ADDAPB1SPEN":
+    "*EN":
+      Disable: [0, "Disable the selected module in sleep mode."]
+      Enable: [1, "Enable the selected module in sleep mode."]
+  ADDAPB1RST:
+    "*RST":
+      Reset: [1, "Reset the selected module"]
+  ADDAPB1EN:
+    "*EN":
+      Disabled: [0, "The selected clock is disabled"]
+      Enabled: [1, "The selected clock is enabled"]
+  BDCTL:
+    BKPRST:
+      NoReset: [0, "Reset not activated"]
+      Reset: [1, "Reset the entire RTC domain"]
+    RTCEN:
+      Disabled: [0, "RTC clock disabled"]
+      Enabled: [1, "RTC clock enabled"]
+    RTCSRC:
+      NoClock: [0, "No clock"]
+      LXTAL: [1, "LXTAL oscillator clock used as RTC clock"]
+      IRC32K: [2, "IRC32K oscillator clock used as RTC clock"]
+      HXTAL: [3, "HXTAL oscillator / RTCDIV (CFG0) used as RTC clock"]
+    LXTALDRI:
+      Low: [0, "Low driving capability (reset value)"]
+      High: [1, "High driving capability"]
+    LXTALBPS:
+      NotBypassed: [0, "LXTAL crystal oscillator not bypassed"]
+      Bypassed: [1, "LXTAL crystal oscillator bypassed with external clock"]
+    LXTALSTB:
+      _read:
+        NotReady: [0, "LXTAL oscillator not ready"]
+        Ready: [1, "LXTAL oscillator ready"]
+    LXTALEN:
+      "Off": [0, "LXTAL oscillator Off"]
+      "On": [1, "LXTAL oscillator On"]
+  RSTSCK:
+    LPRSTF,WWDGTRSTF,FWDGTRSTF,SWRSTF,PORRSTF,EPRSTF,BORRSTF:
+      _read:
+        NoReset: [0, "No reset has occured"]
+        Reset: [1, "A reset has occured"]
+    RSTFC:
+      _write:
+        Clear: [1, "Clears reset flags"]
+    IRC32KSTB:
+      _read:
+        NotReady: [0, "IRC32K oscillator is not stable"]
+        Ready: [1, "IRC32K oscillator is stable"]
+    IRC32KEN:
+      "Off": [0, "IRC32K oscillator disabled"]
+      "On": [1, "IRC32K oscillator enabled"]
+  PLLSSCTL:
+    SSCGON:
+      Enable: [0, "Enable the module."]
+      Disable: [1, "Disable the module."]
+    SS_TYPE:
+      CENTER: [0, "Center spread."]
+      DOWN: [1, "Down spread."]
+  PLLI2S:
+    PLLI2SR:
+      DIV2: [2, "I2S clock frequency divided by 2."]
+      DIV3: [3, "I2S clock frequency divided by 3."]
+      DIV4: [4, "I2S clock frequency divided by 4."]
+      DIV5: [5, "I2S clock frequency divided by 5."]
+      DIV6: [6, "I2S clock frequency divided by 6."]
+      DIV7: [7, "I2S clock frequency divided by 7."]
+  PLLSAI:
+    PLLSAIR:
+      DIV2: [2, "TLI clock frequency is PLLSAIVCO divided by 2."]
+      DIV3: [3, "TLI clock frequency is PLLSAIVCO divided by 3."]
+      DIV4: [4, "TLI clock frequency is PLLSAIVCO divided by 4."]
+      DIV5: [5, "TLI clock frequency is PLLSAIVCO divided by 5."]
+      DIV6: [6, "TLI clock frequency is PLLSAIVCO divided by 6."]
+      DIV7: [7, "TLI clock frequency is PLLSAIVCO divided by 7."]
+    PLLSAIP:
+      DIV2: [0, "PLLSAI P Clock is PLLSAIVCO divided by 2."]
+      DIV4: [1, "PLLSAI P Clock is PLLSAIVCO divided by 4."]
+      DIV6: [2, "PLLSAI P Clock is PLLSAIVCO divided by 6."]
+      DIV8: [3, "PLLSAI P Clock is PLLSAIVCO divided by 8."]
+  CFG1:
+    TIMERSEL:
+      RESET:
+        [
+          0,
+          "If APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). Or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2).",
+        ]
+      SET:
+        [
+          1,
+          "If APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). Or else, the TIMER clock is four times the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4x CK_APB1, TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2).",
+        ]
+    PLLSAIRDIV:
+      DIV2: [0, "TLI clock is CK_PLLSAIR divided by 2."]
+      DIV4: [1, "TLI clock is CK_PLLSAIR divided by 4."]
+      DIV8: [2, "TLI clock is CK_PLLSAIR divided by 8."]
+      DIV16: [3, "TLI clock is CK_PLLSAIR divided by 16."]
+  ADDCTL:
+    IRC48MSTB:
+      _read:
+        NotReady: [0, "IRC48M oscillator is not stable."]
+        Ready: [1, "IRC48M oscillator is stable."]
+    IRC48MEN:
+      "Off": [0, "IRC48M Clock off."]
+      "On": [1, "IRC48M Clock on."]
+    PLL48MSEL:
+      PLLQ: [0, "Select the PLLQ clock."]
+      PLLSAIP: [1, "Select the PLLSAIP clock."]
+    CK48MSEL:
+      None:
+        [0, "Don’t select IRC48M clock(use CK_PLLQ clock or CK_PLLSAIP clock select by PLL48MSEL)"]
+      IRC48M: [1, "Select the IRC48M clock."]
+  ADDINT:
+    IRC48MSTBIC:
+      _write:
+        Clear: [1, "Clear PLLSTBIF flag"]
+    IRC48MSTBIE:
+      Disabled: [0, "Interrupt disabled"]
+      Enabled: [1, "Interrupt enabled"]
+    IRC48MSTBIF:
+      _read:
+        NotInterrupted: [0, "No interrupt generated"]
+        Interrupted: [1, "PLL stabilisation interrupt generated"]
+  DSV:
+    DSLPVS:
+      Default: [0, "The core voltage is default value in Deep-sleep mode"]
+      Default10Pct:
+        [
+          1,
+          "The core voltage is (default value-0.1)V in Deep-sleep mode(customers are not recommended to use it)",
+        ]
+      Default20Pct:
+        [
+          2,
+          "The core voltage is (default value-0.2)V in Deep-sleep mode(customers are not recommended to use it)",
+        ]
+      Default30Pct:
+        [
+          3,
+          "The core voltage is (default value-0.3)V in Deep-sleep mode(customers are not recommended to use it)",
+        ]

From c572b7e15604d95d23c1b845ed7a86d1832fed6b Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 14:38:19 +0800
Subject: [PATCH 02/22] Add gpio f4

---
 peripherals/gpio/gpio_f4.yaml | 71 +++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 peripherals/gpio/gpio_f4.yaml

diff --git a/peripherals/gpio/gpio_f4.yaml b/peripherals/gpio/gpio_f4.yaml
new file mode 100644
index 000000000..0b6667986
--- /dev/null
+++ b/peripherals/gpio/gpio_f4.yaml
@@ -0,0 +1,71 @@
+# Copyright 2021 The gd32-rs authors.
+#
+# SPDX-License-Identifier: MIT OR Apache-2.0
+
+"GPIO*":
+  CTL:
+    "CTL*":
+      Input: [0, "Input mode (reset state)"]
+      Output: [1, "General purpose output mode"]
+      Alternate: [2, "Alternate function mode"]
+      Analog: [3, "Analog mode"]
+  OMODE:
+    "OM*":
+      PushPull: [0, "Output push-pull (reset state)"]
+      OpenDrain: [1, "Output open-drain"]
+  OSPD:
+    "OSPD*":
+      Speed2M: [0, "Max output speed 2 MHz"]
+      Speed10M: [1, "Max output speed 10 MHz"]
+      Speed50M: [3, "Max output speed 50 MHz"]
+  PUD:
+    "PUD*":
+      Floating: [0, "No pull-up, pull-down (reset state)"]
+      PullUp: [1, "Pull-up"]
+      PullDown: [2, "Pull-down"]
+  ISTAT:
+    "ISTAT*":
+      Low: [0, "Input is logic low"]
+      High: [1, "Input is logic high"]
+  OCTL:
+    "OCTL*":
+      Low: [0, "Set output to logic low"]
+      High: [1, "Set output to logic high"]
+  BOP:
+    "CR*":
+      _write:
+        Reset: [1, "Resets the corresponding OCTLx bit"]
+    "BOP*":
+      _write:
+        Set: [1, "Sets the corresponding OCTLx bit"]
+  LOCK:
+    LKK:
+      NotActive: [0, "Register not locked and port configuration can be changed."]
+      Active: [1, "Register locked and port configuration can not be changed."]
+    "LK[0-15]":
+      Unlocked: [0, "Corresponding bit port configuration not locked"]
+      Locked: [1, "Corresponding bit port configuration locked"]
+  BC:
+    "CR*":
+      _write:
+        Reset: [1, "Resets the corresponding OCTLx bit"]
+  TG:
+    "TG*":
+      _write:
+        Toggle: [1, "Toggles the corresponding OCTLx bit"]
+  AFSEL[01]:
+    "SEL*":
+      AF0: [0, "AF0"]
+      AF1: [1, "AF1"]
+      AF2: [2, "AF2"]
+      AF3: [3, "AF3"]
+      AF4: [4, "AF4"]
+      AF5: [5, "AF5"]
+      AF6: [6, "AF6"]
+      AF7: [7, "AF7"]
+      AF9: [9, "AF9"]
+      AF11: [11, "AF11"]
+      AF12: [12, "AF12"]
+      AF13: [13, "AF13"]
+      AF14: [14, "AF14"]
+      AF15: [15, "AF15"]

From c81838474b4d28da06c894d1f3eddbd4ea5dc950 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 14:39:41 +0800
Subject: [PATCH 03/22] Adding gpio peripheral patches

---
 devices/gd32f425.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index 9bf1ed102..983c8c8fb 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -9,3 +9,4 @@ _modify:
 _include:
   - common_patches/gd32f425.yaml
   - ../peripherals/rcu/rcu_f4.yaml
+  - ../peripherals/gpio/gpio_f4.yaml

From 38d991e53c483fffb04399231bf95bb4aa0e542b Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 22:43:31 +0800
Subject: [PATCH 04/22] Adding PMU peripheral register docs

---
 devices/gd32f425.yaml       |  1 +
 peripherals/pmu/pmu_f4.yaml | 86 +++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)
 create mode 100644 peripherals/pmu/pmu_f4.yaml

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index 983c8c8fb..a6a2f98d2 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -8,5 +8,6 @@ _modify:
   name: "GD32F425"
 _include:
   - common_patches/gd32f425.yaml
+  - ../peripherals/adc/pmu_f4.yaml
   - ../peripherals/rcu/rcu_f4.yaml
   - ../peripherals/gpio/gpio_f4.yaml
diff --git a/peripherals/pmu/pmu_f4.yaml b/peripherals/pmu/pmu_f4.yaml
new file mode 100644
index 000000000..8456e8223
--- /dev/null
+++ b/peripherals/pmu/pmu_f4.yaml
@@ -0,0 +1,86 @@
+PMU:
+  CTL:
+    BKPWEN:
+      Disabled: [0, "Access to backup domain registers disabled"]
+      Enabled: [1, "Access to backup domain registers enabled"]
+    LVDT:
+      V2_1: [0, "2.1 V"]
+      V2_3: [1, "2.3 V"]
+      V2_4: [2, "2.4 V"]
+      V2_6: [3, "2.6 V"]
+      V2_7: [4, "2.7 V"]
+      V2_9: [5, "2.9 V"]
+      V3_0: [6, "3.0 V"]
+      V3_1: [7, "3.1 V"]
+    LVDEN:
+      Disabled: [0, "Low voltage detector disabled"]
+      Enabled: [1, "Low voltage detector enabled"]
+    STBRST:
+      _write:
+        Clear: [1, "Clear the standby flag"]
+    WURST:
+      _write:
+        Clear: [1, "Clear the wakeup flag"]
+    STBMOD:
+      DeepSleep: [0, "Enter Deep-sleep mode when the CPU enters deepsleep"]
+      Standby: [1, "Enter Standby mode when the CPU enters deepsleep"]
+    LDOLP:
+      Normal: [0, "LDO operates normally during Deepsleep mode"]
+      LowPower: [1, "LDO in low-power mode during Deepsleep mode"]
+    LDOVS:
+      LowMode: [1, "LDO output voltage low mode"]
+      MidMode: [2, "LDO output voltage mid mode"]
+      HighMode: [3, "LDO output voltage high mode"]
+    LDEN:
+      Disabled: [0, "Low-driver mode disabled in Deep-sleep mode"]
+      Enabled: [3, "Low-driver mode enabled in Deep-sleep mode"]
+    HDS:
+      NoSwitch: [0, "No high-driver mode switch"]
+      Switch: [1, "High-driver mode switch enabled"]
+    HDEN:
+      Disabled: [0, "High-driver mode disabled"]
+      Enabled: [1, "High-driver mode enabled"]
+    LDNP:
+      NormalDriver: [0, "Normal-driver mode with normal power LDO"]
+      LowDriver: [1, "Low-driver mode enabled with normal power LDO"]
+    LDLP:
+      NormalDriver: [0, "Normal-driver mode with low power LDO"]
+      LowDriver: [1, "Low-driver mode enabled with low power LDO"]
+  CS:
+    LDRF:
+      NormalDriver: [0, "Normal driver in Deep-sleep mode"]
+      LowDriver: [3, "Low-driver mode in Deep-sleep mode"]
+    HDSRF:
+      _read:
+        NotReady: [0, "High-driver switch not ready"]
+        Ready: [1, "High-driver switch ready"]
+    HDRF:
+      _read:
+        NotReady: [0, "High-driver not ready"]
+        Ready: [1, "High-driver ready"]
+    LDOVSRF:
+      _read:
+        NotReady: [0, "LDO voltage select not ready"]
+        Ready: [1, "LDO voltage select ready"]
+    BLDOON:
+      Closed: [0, "Backup SRAM LDO closed"]
+      Open: [1, "Open the Backup SRAM LDO"]
+    WUPEN:
+      Disabled: [0, "WKUP pin function disabled"]
+      Enabled: [1, "WKUP pin function enabled"]
+    BLDORF:
+      _read:
+        NotReady: [0, "Backup SRAM LDO not ready"]
+        Ready: [1, "Backup SRAM LDO ready"]
+    LVDF:
+      _read:
+        NoEvent: [0, "No Low Voltage event occurred (VDD > threshold)"]
+        EventOccurred: [1, "Low Voltage event occurred (VDD ≤ threshold)"]
+    STBF:
+      _read:
+        NotEntered: [0, "The device has not entered Standby mode"]
+        Entered: [1, "The device has been in Standby mode"]
+    WUF:
+      _read:
+        NoEvent: [0, "No wakeup event received"]
+        EventOccurred: [1, "Wakeup event occurred"]

From c6ffda0f7818a4fe733ce8a9cfaa298af8ac97e7 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 22:46:34 +0800
Subject: [PATCH 05/22] Adding PMU peripheral register docs

---
 devices/gd32f425.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index a6a2f98d2..8ffeb223f 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -8,6 +8,6 @@ _modify:
   name: "GD32F425"
 _include:
   - common_patches/gd32f425.yaml
-  - ../peripherals/adc/pmu_f4.yaml
+  - ../peripherals/pmu/pmu_f4.yaml
   - ../peripherals/rcu/rcu_f4.yaml
   - ../peripherals/gpio/gpio_f4.yaml

From 509568a701e6f5af2ced811401fcb017b5eae58d Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 22:56:31 +0800
Subject: [PATCH 06/22] Add the CTC CTL0 register

---
 peripherals/ctc/ctc_f4.yaml | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 peripherals/ctc/ctc_f4.yaml

diff --git a/peripherals/ctc/ctc_f4.yaml b/peripherals/ctc/ctc_f4.yaml
new file mode 100644
index 000000000..6b986f60b
--- /dev/null
+++ b/peripherals/ctc/ctc_f4.yaml
@@ -0,0 +1,22 @@
+CTC:
+  CTL0:
+    SWREFPUL:
+      "Generate": [1, "Generates a software reference source sync pulse."]
+    AUTOTRIM:
+      Disabled: [0, "Hardware automatic trim disabled"]
+      Enabled: [1, "Hardware automatic trim enabled"]
+    CNTEN:
+      Disabled: [0, "CTC trim counter disabled"]
+      Enabled: [1, "CTC trim counter enabled"]
+    EREFIE:
+      Disabled: [0, "EREFIF interrupt disabled"]
+      Enabled: [1, "EREFIF interrupt enabled"]
+    ERRIE:
+      Disabled: [0, "ERRIF interrupt disabled"]
+      Enabled: [1, "ERRIF interrupt enabled"]
+    CKWARNIE:
+      Disabled: [0, "CKWARNIF interrupt disabled"]
+      Enabled: [1, "CKWARNIF interrupt enabled"]
+    CKOKIE:
+      Disabled: [0, "CKOKIF interrupt disabled"]
+      Enabled: [1, "CKOKIF interrupt enabled"]

From d927fd3965f319f8158281020ef895ffa7a91002 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:00:07 +0800
Subject: [PATCH 07/22] Add fields for CTL1

---
 peripherals/ctc/ctc_f4.yaml | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/peripherals/ctc/ctc_f4.yaml b/peripherals/ctc/ctc_f4.yaml
index 6b986f60b..28cc8adac 100644
--- a/peripherals/ctc/ctc_f4.yaml
+++ b/peripherals/ctc/ctc_f4.yaml
@@ -20,3 +20,21 @@ CTC:
     CKOKIE:
       Disabled: [0, "CKOKIF interrupt disabled"]
       Enabled: [1, "CKOKIF interrupt enabled"]
+  CTL1:
+    REFPOL:
+      RisingEdge: [0, "Rising edge selected"]
+      FallingEdge: [1, "Falling edge selected"]
+    REFSEL:
+      GPIO: [0, "GPIO (CTC_SYNC) selected"]
+      LXTAL: [1, "LXTAL clock selected"]
+      Reserved1: [2, "Reserved"]
+      Reserved2: [3, "Reserved"]
+    REFPSC:
+      DIV1: [0, "Reference signal not divided"]
+      DIV2: [1, "Reference signal divided by 2"]
+      DIV4: [2, "Reference signal divided by 4"]
+      DIV8: [3, "Reference signal divided by 8"]
+      DIV16: [4, "Reference signal divided by 16"]
+      DIV32: [5, "Reference signal divided by 32"]
+      DIV64: [6, "Reference signal divided by 64"]
+      DIV128: [7, "Reference signal divided by 128"]

From 9e87de8bbdb344bb3b60325b026e9d5a5ba3cc47 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:02:05 +0800
Subject: [PATCH 08/22] Add fields for STAT

---
 peripherals/ctc/ctc_f4.yaml | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/peripherals/ctc/ctc_f4.yaml b/peripherals/ctc/ctc_f4.yaml
index 28cc8adac..ca0588846 100644
--- a/peripherals/ctc/ctc_f4.yaml
+++ b/peripherals/ctc/ctc_f4.yaml
@@ -38,3 +38,28 @@ CTC:
       DIV32: [5, "Reference signal divided by 32"]
       DIV64: [6, "Reference signal divided by 64"]
       DIV128: [7, "Reference signal divided by 128"]
+  STAT:
+    REFDIR:
+      Up: [0, "CTC trim counter up-counting"]
+      Down: [1, "CTC trim counter down-counting"]
+    TRIMERR:
+      NoError: [0, "No trim value error occurs"]
+      ErrorOccurred: [1, "Trim value error occurs"]
+    REFMISS:
+      NoMiss: [0, "No reference sync pulse miss occurs"]
+      MissOccurred: [1, "Reference sync pulse miss occurs"]
+    CKERR:
+      NoError: [0, "No clock trim error occurs"]
+      ErrorOccurred: [1, "Clock trim error occurs"]
+    EREFIF:
+      NoReference: [0, "No expected reference occurs"]
+      ReferenceOccurred: [1, "Expected reference occurs"]
+    ERRIF:
+      NoError: [0, "No error occurs"]
+      ErrorOccurred: [1, "An error occurs"]
+    CKWARNIF:
+      NoWarning: [0, "No clock trim warning occurs"]
+      WarningOccurred: [1, "Clock trim warning occurs"]
+    CKOKIF:
+      NotOK: [0, "No clock trim OK occurs"]
+      OK: [1, "Clock trim OK occurs"]

From 40bb42b0c76f4b6e3d2b0838a1cd7a56fe37c03f Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:03:58 +0800
Subject: [PATCH 09/22] Add fields for INTC

---
 peripherals/ctc/ctc_f4.yaml | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/peripherals/ctc/ctc_f4.yaml b/peripherals/ctc/ctc_f4.yaml
index ca0588846..6bac343d7 100644
--- a/peripherals/ctc/ctc_f4.yaml
+++ b/peripherals/ctc/ctc_f4.yaml
@@ -63,3 +63,16 @@ CTC:
     CKOKIF:
       NotOK: [0, "No clock trim OK occurs"]
       OK: [1, "Clock trim OK occurs"]
+  INTC:
+    EREFIC:
+      _write:
+        Clear: [1, "Clear the EREFIF bit in CTC_STAT register"]
+    ERRIC:
+      _write:
+        Clear: [1, "Clear ERRIF, TRIMERR, REFMISS, and CKERR bits in CTC_STAT register"]
+    CKWARNIC:
+      _write:
+        Clear: [1, "Clear CKWARNIF bit in CTC_STAT register"]
+    CKOKIC:
+      _write:
+        Clear: [1, "Clear CKOKIF bit in CTC_STAT register"]

From db9f26ab2ad30a3f27d57d0d286e4e69d288cd03 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:04:40 +0800
Subject: [PATCH 10/22] Add ctc to includes

---
 devices/gd32f425.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index 8ffeb223f..c0883fedb 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -10,4 +10,5 @@ _include:
   - common_patches/gd32f425.yaml
   - ../peripherals/pmu/pmu_f4.yaml
   - ../peripherals/rcu/rcu_f4.yaml
+  - ../peripherals/ctc/ctc_f4.yaml
   - ../peripherals/gpio/gpio_f4.yaml

From 5a8969e0dfe128d6e4030bfd7a6d1ec7f001d2c9 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:07:23 +0800
Subject: [PATCH 11/22] EXTI peripheral can be added without modifications

---
 devices/gd32f425.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index c0883fedb..c3ba946dd 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -12,3 +12,4 @@ _include:
   - ../peripherals/rcu/rcu_f4.yaml
   - ../peripherals/ctc/ctc_f4.yaml
   - ../peripherals/gpio/gpio_f4.yaml
+  - ../peripherals/exti/exti.yaml

From 70c71143a1b170fb0a9921aedc91b10e3b3ce32d Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:09:03 +0800
Subject: [PATCH 12/22] CRC peripheral can be added without modifications

---
 devices/gd32f425.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index c3ba946dd..8c31410fd 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -13,3 +13,4 @@ _include:
   - ../peripherals/ctc/ctc_f4.yaml
   - ../peripherals/gpio/gpio_f4.yaml
   - ../peripherals/exti/exti.yaml
+  - ../peripherals/crc/crc.yaml

From f1aa53c9f7d9a3a0e6a461f2b6566f89da6e117c Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Thu, 12 Sep 2024 23:14:43 +0800
Subject: [PATCH 13/22] Adding the TRNG peripheral

---
 devices/gd32f425.yaml      |  1 +
 peripherals/trng/trng.yaml | 41 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 peripherals/trng/trng.yaml

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index 8c31410fd..cdd29d50e 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -14,3 +14,4 @@ _include:
   - ../peripherals/gpio/gpio_f4.yaml
   - ../peripherals/exti/exti.yaml
   - ../peripherals/crc/crc.yaml
+  - ../peripherals/trng/trng.yaml
diff --git a/peripherals/trng/trng.yaml b/peripherals/trng/trng.yaml
new file mode 100644
index 000000000..859b67400
--- /dev/null
+++ b/peripherals/trng/trng.yaml
@@ -0,0 +1,41 @@
+TRNG:
+  CTL:
+    TRNGIE:
+      Disable: [0, "Disable TRNG interrupt"]
+      Enable: [1, "Enable TRNG interrupt"]
+    TRNGEN:
+      Disable: [0, "Disable TRNG"]
+      Enable: [1, "Enable TRNG"]
+  STAT:
+    SEIF:
+      _read:
+        NoFault: [0, "No fault detected"]
+        Fault: [1, "Seed error has been detected. The bit is cleared by writing 0."]
+      _write:
+        Clear: [0, "Clear the SEIF flag"]
+    CEIF:
+      _read:
+        NoFault: [0, "No fault detected"]
+        Fault: [1, "Clock error has been detected. The bit is cleared by writing 0."]
+      _write:
+        Clear: [0, "Clear the CEIF flag"]
+    SECS:
+      _read:
+        NotReady: [0, "The seed is not ready"]
+        Ready: [1, "The seed is ready"]
+    CECS:
+      _read:
+        NotReady:
+          [
+            0,
+            "Clock error is not detected at current time. In case of CEIF=1 and CECS=0, it means clock error has been detected before but now is recovered.",
+          ]
+        Ready:
+          [
+            1,
+            "Clock error is detected at current time. TRNG_CLK frequency is lower than 1/HCLK frequency",
+          ]
+    DRDY:
+      _read:
+        NotReady: [0, "Data is not ready"]
+        Ready: [1, "Data is ready"]

From 8e73a6c324ccd19a880b79e1540c1834bab86ea5 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Fri, 13 Sep 2024 23:43:28 +0800
Subject: [PATCH 14/22] Add rest of DMA registers

---
 peripherals/dma/dma_f4.yaml | 142 ++++++++++++++++++++++++++++++++++++
 1 file changed, 142 insertions(+)
 create mode 100644 peripherals/dma/dma_f4.yaml

diff --git a/peripherals/dma/dma_f4.yaml b/peripherals/dma/dma_f4.yaml
new file mode 100644
index 000000000..0ab9b617b
--- /dev/null
+++ b/peripherals/dma/dma_f4.yaml
@@ -0,0 +1,142 @@
+DMA*:
+  INTF*:
+    FTFIFx:
+      _read:
+        NotComplete: [0, "No transfer complete event"]
+        Complete: [1, "A transfer complete event has occured"]
+      _write:
+        Clear: [0, "Clears flag."]
+    HTFIF*:
+      _read:
+        NotHalf: [0, "No half transfer event"]
+        Half: [1, "A half transfer event has occured"]
+      _write:
+        Clear: [0, "Clears the flag."]
+    TAEIF*:
+      _read:
+        NoError: [0, "No transfer error"]
+        Error: [1, "A transfer error has occured"]
+      _write:
+        Clear: [0, "Clears the flag."]
+    SDEIF*:
+      _read:
+        NoError: [0, "No transfer error"]
+        Error: [1, "A transfer error has occured"]
+      _write:
+        Clear: [0, "Clears the flag."]
+    FEEIF*:
+      _read:
+        NoError: [0, "No FIFO error"]
+        Error: [1, "A FIFO error has occured"]
+      _write:
+        Clear: [0, "Clears the flag."]
+  INTC*:
+    FTFIFC*:
+      _write:
+        Clear: [1, "Clears the FTFIFx flag in INTF."]
+    HTFIFC*:
+      _write:
+        Clear: [1, "Clears the HTFIFx flag in INTF."]
+    TAEIFC*:
+      _write:
+        Clear: [1, "Clears the TAEIFx flag in INTF."]
+    SDEIFC*:
+      _write:
+        Clear: [1, "Clears the SDEIFx flag in INTF."]
+    FEEIFC*:
+      _write:
+        Clear: [1, "Clears the FEEIFx flag in INTF."]
+  CH*CTL:
+    PERIEN:
+      P0: [0, "Enable Peripheral 0"]
+      P1: [1, "Enable Peripheral 1"]
+      P2: [2, "Enable Peripheral 2"]
+      P3: [3, "Enable Peripheral 3"]
+      P4: [4, "Enable Peripheral 4"]
+      P5: [5, "Enable Peripheral 5"]
+      P6: [6, "Enable Peripheral 6"]
+      P7: [7, "Enable Peripheral 7"]
+    MBURST:
+      Single: [0, "Single transfer"]
+      INCR4: [1, "Incremental burst of 4 beats"]
+      INCR8: [2, "Incremental burst of 8 beats"]
+      INCR16: [3, "Incremental burst of 16 beats"]
+    PBURST:
+      Single: [0, "Single transfer"]
+      INCR4: [1, "Incremental burst of 4 beats"]
+      INCR8: [2, "Incremental burst of 8 beats"]
+      INCR16: [3, "Incremental burst of 16 beats"]
+    MBS:
+      Zero: [0, "Memory 0 is selected as the memory transfer area"]
+      One: [1, "Memory 1 is selected as the memory transfer area"]
+    SBMEN:
+      Disabled: [0, "Switch buffer mode disabled"]
+      Enabled: [1, "Switch buffer mode enabled"]
+    PRIO:
+      Low: [0, "Low priority"]
+      Medium: [1, "Medium priority"]
+      High: [2, "High priority"]
+      VeryHigh: [3, "Ultra high priority"]
+    PAIF:
+      PWIDTH: [0, "THe peripheral address increment is determined by the PWIDTH field"]
+      Fixed: [1, "The peripheral address increment is fixed to 4"]
+    MWIDTH:
+      Width8: [0, "8-bit width"]
+      Width16: [1, "16-bit width"]
+      Width32: [2, "32-bit width"]
+    PWIDTH:
+      Width8: [0, "8-bit width"]
+      Width16: [1, "16-bit width"]
+      Width32: [2, "32-bit width"]
+    PNAGA:
+      Fixed: [0, "Fixed Address generation mode."]
+      Increment: [1, "Increment Address generation mode."]
+    CMEN:
+      Disabled: [0, "Circular mode disabled"]
+      Enabled: [1, "Circular mode enabled"]
+    TM:
+      Periph2Mem: [0, "Peripheral to memory"]
+      Mem2Periph: [1, "Memory to peripheral"]
+      Mem2Mem: [2, "Memory to memory"]
+    TFCS:
+      DMA: [0, "DMA is selected as the transfer flow controller"]
+      Peripheral: [1, "Peripheral is selected as the transfer flow controller"]
+    FTFIE:
+      Disabled: [0, "Transfer complete interrupt disabled"]
+      Enabled: [1, "Transfer complete interrupt enabled"]
+    HTFIE:
+      Disabled: [0, "Half transfer interrupt disabled"]
+      Enabled: [1, "Half transfer interrupt enabled"]
+    SDEIE:
+      Disabled: [0, "Single data mode exception interrupt disabled"]
+      Enabled: [1, "Single data mode exception interrupt enabled"]
+    CHEN:
+      Disabled: [0, "Channel disabled"]
+      Enabled: [1, "Channel enabled"]
+  "CH*CNT":
+    CNT: [0, 0xFFFF]
+  "CH*PADDR":
+    PADDR: [0, 0xFFFFFFFF]
+  "CH*M0ADDR":
+    M0ADDR: [0, 0xFFFFFFFF]
+  "CH*M1ADDR":
+    M1ADDR: [0, 0xFFFFFFFF]
+  "CH*FCTL":
+    FEEIE:
+      Disabled: [0, "FIFO error interrupt disabled"]
+      Enabled: [1, "FIFO error interrupt enabled"]
+    FCNT:
+      NoData: [0, "No data in FIFO"]
+      Words1: [1, "1 word of data in FIFO"]
+      Words2: [2, "2 words of data in FIFO"]
+      Words3: [3, "3 words of data in FIFO"]
+      Empty: [4, "FIFO is empty"]
+      Full: [5, "FIFO is full"]
+    MDMEN:
+      Disabled: [0, "Multi-data mode disabled"]
+      Enabled: [1, "Multi-data mode enabled"]
+    FCCV:
+      Words1: [0, "1 word of data is critical value"]
+      Words2: [1, "2 words of data is critical value"]
+      Words3: [2, "3 words of data is critical value"]
+      Words4: [3, "4 words of data is critical value"]

From e6a008550634a7daaa62800b8c496c3377b78bf9 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Fri, 13 Sep 2024 23:43:56 +0800
Subject: [PATCH 15/22] Add DMA peripheral

---
 devices/gd32f425.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index cdd29d50e..dff19ceba 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -15,3 +15,4 @@ _include:
   - ../peripherals/exti/exti.yaml
   - ../peripherals/crc/crc.yaml
   - ../peripherals/trng/trng.yaml
+  - ../peripherals/dma/dma.yaml

From 6e0eb5af87dcb9a9530c55d85f6e4a957664eab2 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Sat, 14 Sep 2024 09:58:58 +0800
Subject: [PATCH 16/22] adding debug peripheral registers

---
 devices/gd32f425.yaml       |  1 +
 peripherals/dbg/dbg_f4.yaml | 44 +++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 peripherals/dbg/dbg_f4.yaml

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index dff19ceba..dcec5ffbc 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -16,3 +16,4 @@ _include:
   - ../peripherals/crc/crc.yaml
   - ../peripherals/trng/trng.yaml
   - ../peripherals/dma/dma.yaml
+  - ../peripherals/dbg/dbg_f4.yaml
diff --git a/peripherals/dbg/dbg_f4.yaml b/peripherals/dbg/dbg_f4.yaml
new file mode 100644
index 000000000..e3a60c58a
--- /dev/null
+++ b/peripherals/dbg/dbg_f4.yaml
@@ -0,0 +1,44 @@
+DBG:
+  ID:
+    ID_CODE: [0, 0xFFFFFFFF]
+  CTL0:
+    TRACE_IOEN:
+      Disabled: [0, "Trace pin allocation disabled"]
+      Enabled: [1, "Trace pin allocation enabled"]
+    STB_HOLD:
+      Disabled: [0, "No effect"]
+      Enabled:
+        [
+          1,
+          "In standby mode the AHB clock and system clock are provided by IRC16M, a system reset generated when exiting standby mode.",
+        ]
+    DSLP_HOLD:
+      Disabled: [0, "No effect"]
+      Enabled:
+        [
+          1,
+          "In deep-sleep mode the AHB clock and system clock are provided by IRC16M, a system reset generated when exiting deep-sleep mode.",
+        ]
+    SLP_HOLD:
+      Disabled: [0, "No effect"]
+      Enabled: [1, "In sleep mode the AHB clock is on"]
+  CTL1:
+    "CAN*_HOLD":
+      Continue: [0, "Continue running the CAN as usual"]
+      Stop: [1, "Hold the CAN for debug when the core is halted"]
+    "I2C*_HOLD":
+      Continue: [0, "Continue running I2C as usual"]
+      Stop: [1, "Hold the I2C timeout for debug when the core is halted"]
+    "TIMER*_HOLD":
+      Continue: [0, "Continue running the timer as usual"]
+      Stop: [1, "Hold the timer counter for debug when the core is halted"]
+    FWDGT_HOLD:
+      Continue: [0, "Continue running the free watchdog timer as usual"]
+      Stop: [1, "Hold the free watchdog timer for debug when the core is halted"]
+    RTC_HOLD:
+      Continue: [0, "Continue running the RTC as usual"]
+      Stop: [1, "Hold the RTC for debug when the core is halted"]
+  CTL2:
+    "TIMER*_HOLD":
+      Continue: [0, "Continue running the timer as usual"]
+      Stop: [1, "Hold the timer counter for debug when the core is halted"]

From 9b47525fd640952daa9af6c32380e807c795e276 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Sat, 14 Sep 2024 10:02:36 +0800
Subject: [PATCH 17/22] adding iref peripheral registers

---
 devices/gd32f425.yaml         |  1 +
 peripherals/iref/iref_f4.yaml | 14 ++++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 peripherals/iref/iref_f4.yaml

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index dcec5ffbc..dbec62e3d 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -17,3 +17,4 @@ _include:
   - ../peripherals/trng/trng.yaml
   - ../peripherals/dma/dma.yaml
   - ../peripherals/dbg/dbg_f4.yaml
+  - ../peripherals/iref/iref_f4.yaml
diff --git a/peripherals/iref/iref_f4.yaml b/peripherals/iref/iref_f4.yaml
new file mode 100644
index 000000000..9c0256a16
--- /dev/null
+++ b/peripherals/iref/iref_f4.yaml
@@ -0,0 +1,14 @@
+CTL:
+  CREN:
+    Disabled: [0, "Current reference disabled"]
+    Enabled: [1, "Current reference enabled"]
+  SSEL:
+    UA1: [0, "Low power, 1uA step."]
+    UA8: [1, "High current, 8uA step."]
+  CPT:
+    PRECISION: [0, 0x1F]
+  SCMOD:
+    Source: [0, "Source current mode"]
+    Sink: [1, "Sink current mode"]
+  CSDT:
+    CurrentStep: [0, 0x3F]

From f36c8bfc3882b8957868aed7c66e72a5a25ae076 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Sat, 14 Sep 2024 10:09:48 +0800
Subject: [PATCH 18/22] Adding ADC registers for f4.

---
 peripherals/adc/adc_f4.yaml | 56 +++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 peripherals/adc/adc_f4.yaml

diff --git a/peripherals/adc/adc_f4.yaml b/peripherals/adc/adc_f4.yaml
new file mode 100644
index 000000000..8861f422c
--- /dev/null
+++ b/peripherals/adc/adc_f4.yaml
@@ -0,0 +1,56 @@
+ADC*:
+  STAT:
+    ROVF:
+      _read:
+        NoOverrun: [0, "No overrun occurred in routine data register"]
+        Overrun: [1, "Overrun overrun occurred in routine data register"]
+      _write:
+        Clear: [0, "Clear the routine data register overrun flag"]
+    STRC:
+      _read:
+        NotStarted: [0, "No regular channel conversion started"]
+        Started: [1, "Regular channel conversion has started"]
+      _write:
+        Clear: [0, "Clear the regular channel start flag"]
+    EOC:
+      _read:
+        NotComplete: [0, "Conversion is not complete"]
+        Complete: [1, "Conversion complete"]
+      _write:
+        Clear: [0, "Clear end of group conversion flag"]
+    WDE:
+      _read:
+        NoEvent: [0, "No analog watchdog event occurred"]
+        Event: [1, "Analog watchdog event occurred"]
+      _write:
+        Clear: [0, "Clear the analog watchdog event flag"]
+  CTL0:
+    ROVFIE:
+      Disabled: [0, "ROVF interrupt disabled"]
+      Enabled: [1, "ROVF interrupt enabled."]
+    DRES:
+      Bits12: [0, "12-bit resolution"]
+      Bits10: [1, "10-bit resolution"]
+      Bits8: [2, "8-bit resolution"]
+      Bits6: [3, "6-bit resolution"]
+    RWDEN:
+      Disabled: [0, "Analog watchdog disabled"]
+      Enabled: [1, "Analog watchdog enabled"]
+    DISNUM: [0, 7]
+    DISRC:
+      Disabled: [0, "Discontinuous mode on regular channels disabled"]
+      Enabled: [1, "Discontinuous mode on regular channels enabled"]
+    WDSC:
+      All: [0, "Analog watchdog enabled on all channels"]
+      Single: [1, "Analog watchdog enabled on a single channel"]
+    SM:
+      Disabled: [0, "Scan mode disabled"]
+      Enabled: [1, "Scan mode enabled"]
+    WDEIE:
+      Disabled: [0, "WDE interrupt disabled"]
+      Enabled: [1, "WDE interrupt enabled"]
+    EOCIE:
+      Disabled: [0, "EOC interrupt disabled"]
+      Enabled: [1, "EOC interrupt enabled"]
+    WDCHSEL:
+      Channel: [0, 18]

From e9a1d916ea7da5912bd9c4c494b69dffffddc660 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Sat, 14 Sep 2024 10:33:17 +0800
Subject: [PATCH 19/22] Adding ADC registers for f4.

---
 peripherals/adc/adc_f4.yaml | 94 +++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/peripherals/adc/adc_f4.yaml b/peripherals/adc/adc_f4.yaml
index 8861f422c..29474170a 100644
--- a/peripherals/adc/adc_f4.yaml
+++ b/peripherals/adc/adc_f4.yaml
@@ -54,3 +54,97 @@ ADC*:
       Enabled: [1, "EOC interrupt enabled"]
     WDCHSEL:
       Channel: [0, 18]
+  CTL1:
+    SWCRST:
+      NoEffect: [0, "No effect"]
+      Reset: [1, "Start the conversion of a regular channel"]
+    ETMRC:
+      Disable: [0, "Disable external trigger conversion of regular channels"]
+      RisingEdge: [1, "Enable external trigger conversion of regular channels on rising edge"]
+      FallingEdge: [2, "Enable external trigger conversion of regular channels on falling edge"]
+      BothEdges: [3, "Enable external trigger conversion of regular channels on both edges"]
+    ETSRC:
+      Timer0Ch0: [0, "Timer 0 channel 0 event"]
+      Timer0Ch1: [1, "Timer 0 channel 1 event"]
+      Timer0Ch2: [2, "Timer 0 channel 2 event"]
+      Timer1Ch1: [3, "Timer 1 channel 1 event"]
+      Timer1Ch2: [4, "Timer 1 channel 2 event"]
+      Timer1Ch3: [5, "Timer 1 channel 3 event"]
+      Timer1Trgo: [6, "Timer 1 TRGO event"]
+      Timer2Ch0: [7, "Timer 2 channel 0 event"]
+      Timer2Trgo: [8, "Timer 2 TRGO event"]
+      Timer3Ch3: [9, "Timer 3 channel 3 event"]
+      Timer4Ch0: [10, "Timer 4 channel 0 event"]
+      Timer4Ch1: [11, "Timer 4 channel 1 event"]
+      Timer4Ch2: [12, "Timer 4 channel 2 event"]
+      Timer7Ch0: [13, "Timer 7 channel 0 event"]
+      Timer7Trgo: [14, "Timer 7 TRGO event"]
+      Exti11: [15, "EXTI line 11 event"]
+    DAL:
+      Right: [0, "Right alignment"]
+      Left: [1, "Left alignment"]
+    EOCM:
+      EndOfSequence: [0, "EOC bit is set at the end of a sequence of conversions"]
+      EndOfEach: [1, "EOC bit is set at the end of each conversion"]
+    DDM:
+      Disabled: [0, "DMA mode disabled"]
+      Enabled: [1, "DMA mode enabled"]
+    DMA:
+      Disabled: [0, "DMA request disabled"]
+      Enabled: [1, "DMA request enabled"]
+    RSTCLB:
+      _write:
+        Reset: [1, "Initialize calibration register start."]
+      _read:
+        Done: [0, "Calibration register initialized."]
+        Busy: [1, "Calibration register initializing."]
+    CLB:
+      _write:
+        Start: [1, "Start calibration"]
+      _read:
+        Done: [0, "Calibration complete"]
+        Busy: [1, "Calibration in progress"]
+    CTN:
+      Disabled: [0, "Continuous conversion disabled"]
+      Enabled: [1, "Continuous conversion enabled"]
+    ADCON:
+      Disabled: [0, "ADC disabled"]
+      Enabled: [1, "ADC enabled"]
+  "SAMPT?":
+    "SPT*":
+      Cycles3: [0, "Channel sample time is 3 cycles"]
+      Cycles15: [1, "Channel sample time is 15 cycles"]
+      Cycles28: [2, "Channel sample time is 28 cycles"]
+      Cycles56: [3, "Channel sample time is 56 cycles"]
+      Cycles84: [4, "Channel sample time is 84 cycles"]
+      Cycles112: [5, "Channel sample time is 112 cycles"]
+      Cycles144: [6, "Channel sample time is 144 cycles"]
+      Cycles480: [7, "Channel sample time is 480 cycles"]
+  WDHT:
+    WDHT: [0, 0xFFF]
+  WDLT:
+    WDLT: [0, 0xFFF]
+  RSQ0:
+    RL: [0, 7]
+  "RSQ?":
+    "RSQ*": [0, 18]
+  RDATA:
+    RDATA: [0, 0xFFFF]
+  OVSAMPCTL:
+    TOVS:
+      Consecutive: [0, "All oversampled conversaions for a channel are done consecutively"]
+      Separate: [1, "Oversampled conversions for a channel done wit a separate trigger."]
+    OVSS:
+      Shift: [0, 0b1000]
+    OVSR:
+      Times2: [0, 0b0000]
+      Times4: [1, 0b0001]
+      Times8: [2, 0b0010]
+      Times16: [3, 0b0011]
+      Times32: [4, 0b0100]
+      Times64: [5, 0b0101]
+      Times128: [6, 0b0110]
+      Times256: [7, 0b0111]
+    OVSEN:
+      Disabled: [0, "Oversampling disabled"]
+      Enabled: [1, "Oversampling enabled"]

From de2db0ce8a1a2602fa94fb0f276aadeb55519402 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Sat, 14 Sep 2024 15:23:00 +0800
Subject: [PATCH 20/22] Fix build errors

---
 devices/gd32f425.yaml         |  3 ++-
 peripherals/adc/adc_f4.yaml   | 46 +++++++++++++++++------------------
 peripherals/dma/dma_f4.yaml   |  4 +--
 peripherals/iref/iref_f4.yaml | 27 ++++++++++----------
 peripherals/trng/trng.yaml    |  2 +-
 5 files changed, 40 insertions(+), 42 deletions(-)

diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index dbec62e3d..ec966cf42 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -15,6 +15,7 @@ _include:
   - ../peripherals/exti/exti.yaml
   - ../peripherals/crc/crc.yaml
   - ../peripherals/trng/trng.yaml
-  - ../peripherals/dma/dma.yaml
+  - ../peripherals/dma/dma_f4.yaml
   - ../peripherals/dbg/dbg_f4.yaml
   - ../peripherals/iref/iref_f4.yaml
+  - ../peripherals/adc/adc_f4.yaml
diff --git a/peripherals/adc/adc_f4.yaml b/peripherals/adc/adc_f4.yaml
index 29474170a..585950c55 100644
--- a/peripherals/adc/adc_f4.yaml
+++ b/peripherals/adc/adc_f4.yaml
@@ -1,4 +1,4 @@
-ADC*:
+"ADC?":
   STAT:
     ROVF:
       _read:
@@ -52,10 +52,10 @@ ADC*:
     EOCIE:
       Disabled: [0, "EOC interrupt disabled"]
       Enabled: [1, "EOC interrupt enabled"]
-    WDCHSEL:
-      Channel: [0, 18]
+    # WDCHSEL:
+    #   Channel: [0, 18]
   CTL1:
-    SWCRST:
+    SWRCST:
       NoEffect: [0, "No effect"]
       Reset: [1, "Start the conversion of a regular channel"]
     ETMRC:
@@ -120,31 +120,29 @@ ADC*:
       Cycles112: [5, "Channel sample time is 112 cycles"]
       Cycles144: [6, "Channel sample time is 144 cycles"]
       Cycles480: [7, "Channel sample time is 480 cycles"]
-  WDHT:
-    WDHT: [0, 0xFFF]
-  WDLT:
-    WDLT: [0, 0xFFF]
-  RSQ0:
-    RL: [0, 7]
-  "RSQ?":
-    "RSQ*": [0, 18]
-  RDATA:
-    RDATA: [0, 0xFFFF]
+  # WDHT:
+  #   WDHT: [0, 0xFFF]
+  # WDLT:
+  #   WDLT: [0, 0xFFF]
+  # RSQ0:
+  #   RL: [0, 7]
+  # "RSQ?":
+  #   "RSQ*": [0, 18]
   OVSAMPCTL:
     TOVS:
       Consecutive: [0, "All oversampled conversaions for a channel are done consecutively"]
       Separate: [1, "Oversampled conversions for a channel done wit a separate trigger."]
-    OVSS:
-      Shift: [0, 0b1000]
+    # OVSS:
+    #   Shift: [0, 0b1000]
     OVSR:
-      Times2: [0, 0b0000]
-      Times4: [1, 0b0001]
-      Times8: [2, 0b0010]
-      Times16: [3, 0b0011]
-      Times32: [4, 0b0100]
-      Times64: [5, 0b0101]
-      Times128: [6, 0b0110]
-      Times256: [7, 0b0111]
+      Times2: [0b0000, "Oversampling ratio is 2"]
+      Times4: [0b0001, "Oversampling ratio is 4"]
+      Times8: [0b0010, "Oversampling ratio is 8"]
+      Times16: [0b0011, "Oversampling ratio is 16"]
+      Times32: [0b0100, "Oversampling ratio is 32"]
+      Times64: [0b0101, "Oversampling ratio is 64"]
+      Times128: [0b0110, "Oversampling ratio is 128"]
+      Times256: [0b0111, "Oversampling ratio is 256"]
     OVSEN:
       Disabled: [0, "Oversampling disabled"]
       Enabled: [1, "Oversampling enabled"]
diff --git a/peripherals/dma/dma_f4.yaml b/peripherals/dma/dma_f4.yaml
index 0ab9b617b..403c25627 100644
--- a/peripherals/dma/dma_f4.yaml
+++ b/peripherals/dma/dma_f4.yaml
@@ -1,6 +1,6 @@
-DMA*:
+DMA[1-7]:
   INTF*:
-    FTFIFx:
+    FTFIF*:
       _read:
         NotComplete: [0, "No transfer complete event"]
         Complete: [1, "A transfer complete event has occured"]
diff --git a/peripherals/iref/iref_f4.yaml b/peripherals/iref/iref_f4.yaml
index 9c0256a16..0c8e766b9 100644
--- a/peripherals/iref/iref_f4.yaml
+++ b/peripherals/iref/iref_f4.yaml
@@ -1,14 +1,13 @@
-CTL:
-  CREN:
-    Disabled: [0, "Current reference disabled"]
-    Enabled: [1, "Current reference enabled"]
-  SSEL:
-    UA1: [0, "Low power, 1uA step."]
-    UA8: [1, "High current, 8uA step."]
-  CPT:
-    PRECISION: [0, 0x1F]
-  SCMOD:
-    Source: [0, "Source current mode"]
-    Sink: [1, "Sink current mode"]
-  CSDT:
-    CurrentStep: [0, 0x3F]
+IREF:
+  CTL:
+    CREN:
+      Disabled: [0, "Current reference disabled"]
+      Enabled: [1, "Current reference enabled"]
+    SSEL:
+      UA1: [0, "Low power, 1uA step."]
+      UA8: [1, "High current, 8uA step."]
+    CPT: [0, 0x1F]
+    SCMOD:
+      Source: [0, "Source current mode"]
+      Sink: [1, "Sink current mode"]
+    CSDT: [0, 0x3F]
diff --git a/peripherals/trng/trng.yaml b/peripherals/trng/trng.yaml
index 859b67400..42a42a451 100644
--- a/peripherals/trng/trng.yaml
+++ b/peripherals/trng/trng.yaml
@@ -1,6 +1,6 @@
 TRNG:
   CTL:
-    TRNGIE:
+    IE:
       Disable: [0, "Disable TRNG interrupt"]
       Enable: [1, "Enable TRNG interrupt"]
     TRNGEN:

From e2966d53f69670cf338969a6fe217821ab6b6d65 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Mon, 5 May 2025 07:48:48 +0800
Subject: [PATCH 21/22] adding timer peripherals for f425

---
 .gitignore                      |  1 +
 .python-version                 |  1 +
 devices/gd32f425.yaml           |  1 +
 peripherals/timer/timer_f4.yaml | 97 +++++++++++++++++++++++++++++++++
 pyproject.toml                  |  9 +++
 uv.lock                         | 39 +++++++++++++
 6 files changed, 148 insertions(+)
 create mode 100644 .python-version
 create mode 100644 peripherals/timer/timer_f4.yaml
 create mode 100644 pyproject.toml
 create mode 100644 uv.lock

diff --git a/.gitignore b/.gitignore
index f97b17efe..789cbf073 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,6 +8,7 @@
 html/
 mmaps/
 /venv
+.venv
 
 # automatically generated crates
 /gd32*/
diff --git a/.python-version b/.python-version
new file mode 100644
index 000000000..e4fba2183
--- /dev/null
+++ b/.python-version
@@ -0,0 +1 @@
+3.12
diff --git a/devices/gd32f425.yaml b/devices/gd32f425.yaml
index ec966cf42..bfc914f71 100644
--- a/devices/gd32f425.yaml
+++ b/devices/gd32f425.yaml
@@ -19,3 +19,4 @@ _include:
   - ../peripherals/dbg/dbg_f4.yaml
   - ../peripherals/iref/iref_f4.yaml
   - ../peripherals/adc/adc_f4.yaml
+  - ../peripherals/timer/timer_f4.yaml
diff --git a/peripherals/timer/timer_f4.yaml b/peripherals/timer/timer_f4.yaml
new file mode 100644
index 000000000..d8c3c4941
--- /dev/null
+++ b/peripherals/timer/timer_f4.yaml
@@ -0,0 +1,97 @@
+TIMER[1-4]:
+  CTL0:
+    CKDIV:
+      CKDIV0: [0, "Clock division factor 1"]
+      CKDIV1: [1, "Clock division factor 2"]
+      CKDIV2: [2, "Clock division factor 4"]
+    ARSE:
+      Disabled: [0, "The shadow register for CAR is disabled"]
+      Enabled: [1, "The shadow register for CAR is enabled"]
+    CAM:
+      NoCenterAlign: [0, "No Center aligned mode. Direction specified by DIR bit."]
+      CenterAlignCountDownAssert:
+        [
+          1,
+          "Center-aligned and counting down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Only when counting down, CHxF bit can be set.",
+        ]
+      CenterAlignCountUpAssert: [
+          2,
+          "Center-aligned and counting up assert mode. The counter counts under center-
+          aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0
+          register). Only when counting up, CHxF bit can be set.",
+        ]
+      CenterAlignCountUpDownAssert: [
+          3,
+          "Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in
+          TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit
+          can be set.
+          After the counter is enabled, cannot be switched from 0x00 to non 0x00.",
+        ]
+    DIR:
+      Up: [0, "Counter counts up"]
+      Down: [1, "Counter counts down"]
+    SPM:
+      Disabled: [0, "Single pulse mode disabled."]
+      Enabled: [1, "Single pulse mode enabled."]
+    UPDIS:
+      Enabled: [0, "Update event enabled"]
+      Disabled: [1, "Update event disabled"]
+    CEN:
+      Disabled: [0, "Counter disabled"]
+      Enabled: [1, "Counter enabled"]
+  CTL1:
+    TI0S:
+      CH0: [0, "TIMERx_CH0 is selected as channel 0 trigger input"]
+      MULTI:
+        [
+          1,
+          "The result of combinational XOR of TIMERx_CH0, TIMERx_CH1, TIMERx_CH2 is selected as channel 0 trigger input",
+        ]
+    MMC:
+      Mode0: [
+          0,
+          "When a counter reset event occurs, a TRGO trigger signal is output. The
+          counter resert source:
+          Master timer generate a reset
+          the UPG bit in the TIMERx_SWEVG register is set",
+        ]
+      Mode1: [
+          1,
+          "Enable. When a conter start event occurs, a TRGO trigger signal is output. The
+          counter start source :
+          CEN control bit is set
+          The trigger input in pause mode is high",
+        ]
+      Mode2: [
+          2,
+          "When an update event occurs, a TRGO trigger signal is output. The update
+          source depends on UPDIS bit and UPS bit.",
+        ]
+      Mode3: [
+          3,
+          "When a capture or compare pulse event occurs in channel0, a TRGO trigger
+          signal is output.",
+        ]
+      Mode4: [
+          4,
+          "When a compare event occurs, a TRGO trigger signal is output. The compare
+          source is from O0CPRE.",
+        ]
+      Mode5: [
+          5,
+          "When a compare event occurs, a TRGO trigger signal is output. The compare
+          source is from O1CPRE.",
+        ]
+      Mode6: [
+          6,
+          "When a compare event occurs, a TRGO trigger signal is output. The compare
+          source is from O2CPRE.",
+        ]
+      Mode7: [
+          7,
+          "When a compare event occurs, a TRGO trigger signal is output. The compare
+          source is from O3CPRE.",
+        ]
+    DMAS:
+      CaptureOrCompare: [0, "DMA request is generated by capture/compare event"]
+      Update: [1, "DMA request is generated by update event"]
diff --git a/pyproject.toml b/pyproject.toml
new file mode 100644
index 000000000..5ea9408e2
--- /dev/null
+++ b/pyproject.toml
@@ -0,0 +1,9 @@
+[project]
+name = "gd32-rs"
+version = "0.1.0"
+description = "Add your description here"
+readme = "README.md"
+requires-python = ">=3.12"
+dependencies = [
+    "pyyaml>=6.0.2",
+]
diff --git a/uv.lock b/uv.lock
new file mode 100644
index 000000000..8675a2766
--- /dev/null
+++ b/uv.lock
@@ -0,0 +1,39 @@
+version = 1
+requires-python = ">=3.12"
+
+[[package]]
+name = "gd32-rs"
+version = "0.1.0"
+source = { virtual = "." }
+dependencies = [
+    { name = "pyyaml" },
+]
+
+[package.metadata]
+requires-dist = [{ name = "pyyaml", specifier = ">=6.0.2" }]
+
+[[package]]
+name = "pyyaml"
+version = "6.0.2"
+source = { registry = "https://pypi.org/simple" }
+sdist = { url = "https://files.pythonhosted.org/packages/54/ed/79a089b6be93607fa5cdaedf301d7dfb23af5f25c398d5ead2525b063e17/pyyaml-6.0.2.tar.gz", hash = "sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e", size = 130631 }
+wheels = [
+    { url = "https://files.pythonhosted.org/packages/86/0c/c581167fc46d6d6d7ddcfb8c843a4de25bdd27e4466938109ca68492292c/PyYAML-6.0.2-cp312-cp312-macosx_10_9_x86_64.whl", hash = "sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab", size = 183873 },
+    { url = "https://files.pythonhosted.org/packages/a8/0c/38374f5bb272c051e2a69281d71cba6fdb983413e6758b84482905e29a5d/PyYAML-6.0.2-cp312-cp312-macosx_11_0_arm64.whl", hash = "sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725", size = 173302 },
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From 79d0e5ee61e59dc147ea1994eae5c303b729f5b2 Mon Sep 17 00:00:00 2001
From: Ashwin Narayan <ashwinnarayan1994@gmail.com>
Date: Mon, 5 May 2025 08:10:20 +0800
Subject: [PATCH 22/22] Docs for SMCFG register

---
 peripherals/timer/timer_f4.yaml | 86 +++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/peripherals/timer/timer_f4.yaml b/peripherals/timer/timer_f4.yaml
index d8c3c4941..9bb70ec60 100644
--- a/peripherals/timer/timer_f4.yaml
+++ b/peripherals/timer/timer_f4.yaml
@@ -33,6 +33,14 @@ TIMER[1-4]:
     SPM:
       Disabled: [0, "Single pulse mode disabled."]
       Enabled: [1, "Single pulse mode enabled."]
+    UPS:
+      AnyEvent: [
+          0,
+          "Any of counter overflow/underflow, setting UPG, or update through slave
+          mode, generates an update interrupt or DMA request",
+        ]
+      CounterOnly:
+        [1, "Only counter overflow/underflow generates an update interrupt or DMA request"]
     UPDIS:
       Enabled: [0, "Update event enabled"]
       Disabled: [1, "Update event disabled"]
@@ -95,3 +103,81 @@ TIMER[1-4]:
     DMAS:
       CaptureOrCompare: [0, "DMA request is generated by capture/compare event"]
       Update: [1, "DMA request is generated by update event"]
+  SMCFG:
+    ETP:
+      RisingEdge: [0, "ETI is active at rising edge or high level."]
+      FallingEdge: [1, "ETI is active at falling edge or low level."]
+    SMC1:
+      Disabled: [0, "External clock mode 1 disabled."]
+      Enabled:
+        [
+          1,
+          "External clock mode 1 enabled. Counter is clocked by any active edge of the ETIFP signal.",
+        ]
+    ETPSC:
+      PSC0: [0, "Prescale is disabled."]
+      PSC1: [1, "Prescale is divided by 2."]
+      PSC2: [2, "Prescale is divided by 4."]
+      PSC3: [3, "Prescale is divided by 8."]
+    ETFC:
+      Disabled: [0, "ETIFP filter disabled."]
+      CAPACITY1: [1, "ETIFP filter capacity is 2, f_samp is fck_timer"]
+      CAPACITY2: [2, "ETIFP filter capacity is 4, f_samp is fck_timer"]
+      CAPACITY3: [3, "ETIFP filter capacity is 8, f_samp is fck_timer"]
+      CAPACITY4: [4, "ETIFP filter capacity is 6, f_samp is fck_timer / 2"]
+      CAPACITY5: [5, "ETIFP filter capacity is 8, f_samp is fck_timer / 2"]
+      CAPACITY6: [6, "ETIFP filter capacity is 6, f_samp is fck_timer / 4"]
+      CAPACITY7: [7, "ETIFP filter capacity is 8, f_samp is fck_timer / 4"]
+      CAPACITY8: [8, "ETIFP filter capacity is 6, f_samp is fck_timer / 8"]
+      CAPACITY9: [9, "ETIFP filter capacity is 8, f_samp is fck_timer / 8"]
+      CAPACITY10: [10, "ETIFP filter capacity is 5, f_samp is fck_timer / 16"]
+      CAPACITY11: [11, "ETIFP filter capacity is 6, f_samp is fck_timer / 16"]
+      CAPACITY12: [12, "ETIFP filter capacity is 8, f_samp is fck_timer / 16"]
+      CAPACITY13: [13, "ETIFP filter capacity is 5, f_samp is fck_timer / 32"]
+      CAPACITY14: [14, "ETIFP filter capacity is 6, f_samp is fck_timer / 32"]
+      CAPACITY15: [15, "ETIFP filter capacity is 8, f_samp is fck_timer / 32"]
+    MSM:
+      Disabled: [0, "Master/slave mode disabled."]
+      Master: [1, "Master mode enabled."]
+    TRGS:
+      ITI0: [0, "Trigger input is ITI0."]
+      ITI1: [1, "Trigger input is ITI1."]
+      ITI2: [2, "Trigger input is ITI2."]
+      ITI3: [3, "Trigger input is ITI3."]
+      CI0F_EDGE: [4, "Trigger input is CI0F_EDGE."]
+      CI0FE0: [5, "Trigger input is CI0FE0."]
+      CI1FE1: [6, "Trigger input is CI1FE1."]
+      ETIFP: [7, "Trigger input is ETIFP."]
+    SMC:
+      Disabled: [0, "Slave mode disabled."]
+      EncoderMode1: [
+          1,
+          "Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the
+          direction depends on CI1FE1 level.",
+        ]
+      EncoderMode2: [
+          2,
+          "Quadrature decoder mode 1.The counter counts on CI1FE1 edge, while the
+          direction depends on CI0FE0 level.",
+        ]
+      EncoderMode3: [
+          3,
+          "Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1
+          edge, while the direction depends on each other.",
+        ]
+      RestartMode: [
+          4,
+          "Restart mode. The counter is reinitialized and an update event is generated on
+          the rising edge of the selected trigger input.",
+        ]
+      PauseMode: [
+          5,
+          "Pause mode. The trigger input enables the counter clock when it is high and
+          disables the counter clock when it is low.",
+        ]
+      TriggerMode: [6, "Event mode. A rising edge of the trigger input enables the counter."]
+      ExternalClockMode1: [
+          7,
+          "External clock mode 0. The counter counts on the rising edges of the selected
+          trigger.",
+        ]