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robert-hhdpgeorge
robert-hh
authored and
dpgeorge
committed
mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board.
The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
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+3012
-351
lines changed

‎ports/mimxrt/Makefile

+28-13
Original file line numberDiff line numberDiff line change
@@ -101,13 +101,12 @@ SRC_ETH_C += \
101101
hal/phy/device/phydp83848/fsl_phydp83848.c \
102102
hal/phy/device/phyksz8081/fsl_phyksz8081.c \
103103
hal/phy/device/phylan8720/fsl_phylan8720.c \
104+
hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c \
104105
hal/phy/mdio/enet/fsl_enet_mdio.c
105106
endif
106107

107108
# NXP SDK sources
108109
SRC_HAL_IMX_C += \
109-
$(MCU_DIR)/drivers/fsl_adc.c \
110-
$(MCU_DIR)/drivers/fsl_cache.c \
111110
$(MCU_DIR)/drivers/fsl_clock.c \
112111
$(MCU_DIR)/drivers/fsl_common.c \
113112
$(MCU_DIR)/drivers/fsl_dmamux.c \
@@ -124,10 +123,9 @@ SRC_HAL_IMX_C += \
124123
$(MCU_DIR)/drivers/fsl_pwm.c \
125124
$(MCU_DIR)/drivers/fsl_sai.c \
126125
$(MCU_DIR)/drivers/fsl_snvs_lp.c \
127-
$(MCU_DIR)/drivers/fsl_trng.c \
128126
$(MCU_DIR)/drivers/fsl_wdog.c \
129-
$(MCU_DIR)/system_$(MCU_SERIES).c \
130-
hal/fsl_flexspi_nor_boot.c \
127+
$(MCU_DIR)/system_$(MCU_SERIES)$(MCU_CORE).c \
128+
$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
131129

132130
ifeq ($(MICROPY_HW_SDRAM_AVAIL),1)
133131
SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_semc.c
@@ -137,11 +135,29 @@ ifeq ($(MICROPY_PY_MACHINE_SDCARD),1)
137135
SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_usdhc.c
138136
endif
139137

140-
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064))
138+
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
141139
SRC_HAL_IMX_C += \
142140
$(MCU_DIR)/drivers/fsl_qtmr.c
143141
endif
144142

143+
ifeq ($(MCU_SERIES), MIMXRT1176)
144+
INC += -I$(TOP)/$(MCU_DIR)/drivers/cm7
145+
146+
SRC_HAL_IMX_C += \
147+
$(MCU_DIR)/drivers/cm7/fsl_cache.c \
148+
$(MCU_DIR)/drivers/fsl_dcdc.c \
149+
$(MCU_DIR)/drivers/fsl_pmu.c \
150+
$(MCU_DIR)/drivers/fsl_common_arm.c \
151+
$(MCU_DIR)/drivers/fsl_anatop_ai.c \
152+
$(MCU_DIR)/drivers/fsl_caam.c \
153+
$(MCU_DIR)/drivers/fsl_lpadc.c
154+
else
155+
SRC_HAL_IMX_C += \
156+
$(MCU_DIR)/drivers/fsl_adc.c \
157+
$(MCU_DIR)/drivers/fsl_cache.c \
158+
$(MCU_DIR)/drivers/fsl_trng.c
159+
endif
160+
145161
# C source files
146162
SRC_C += \
147163
board_init.c \
@@ -243,7 +259,7 @@ SUPPORTS_HARDWARE_FP_DOUBLE = 0
243259

244260
# Assembly source files
245261
SRC_SS = \
246-
$(MCU_DIR)/gcc/startup_$(MCU_SERIES).S \
262+
$(MCU_DIR)/gcc/startup_$(MCU_SERIES)$(MCU_CORE).S \
247263
hal/resethandler_MIMXRT10xx.S
248264

249265
SRC_S += shared/runtime/gchelper_m3.s \
@@ -279,11 +295,11 @@ CFLAGS += \
279295
-D__STARTUP_INITIALIZE_RAMFUNCTION \
280296
-DBOARD_$(BOARD) \
281297
-DBOARD_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
282-
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX \
298+
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT \
283299
-DCLOCK_CONFIG_H='<boards/$(MCU_SERIES)_clock_config.h>' \
284-
-DCPU_$(MCU_SERIES) \
300+
-DCPU_$(MCU_SERIES)$(MCU_CORE) \
285301
-DCPU_$(MCU_VARIANT) \
286-
-DCPU_HEADER_H='<$(MCU_SERIES).h>' \
302+
-DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \
287303
-DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \
288304
-DI2C_RETRY_TIMES=1000000 \
289305
-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
@@ -438,9 +454,8 @@ $(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h
438454

439455
$(GEN_FLEXRAM_CONFIG_SRC):
440456
$(ECHO) "Create $@"
441-
$(Q)$(PYTHON) $(MAKE_FLEXRAM_LD) -d $(TOP)/$(MCU_DIR)/$(MCU_SERIES).h \
442-
-f $(TOP)/$(MCU_DIR)/$(MCU_SERIES)_features.h -l boards/$(MCU_SERIES).ld -c $(MCU_SERIES) > $(GEN_FLEXRAM_CONFIG_SRC)
443-
457+
$(Q)$(PYTHON) $(MAKE_FLEXRAM_LD) -d $(TOP)/$(MCU_DIR)/$(MCU_SERIES)$(MCU_CORE).h \
458+
-f $(TOP)/$(MCU_DIR)/$(MCU_SERIES)$(MCU_CORE)_features.h -l boards/$(MCU_SERIES).ld -c $(MCU_SERIES) > $(GEN_FLEXRAM_CONFIG_SRC)
444459

445460
# Use a pattern rule here so that make will only call make-pins.py once to make
446461
# both pins_gen.c and pins.h

‎ports/mimxrt/board_init.c

+52-28
Original file line numberDiff line numberDiff line change
@@ -40,51 +40,32 @@
4040
#include CLOCK_CONFIG_H
4141
#include "modmachine.h"
4242

43-
4443
const uint8_t dcd_data[] = { 0x00 };
4544

45+
void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn);
46+
4647
void board_init(void) {
48+
// Clean and enable cache
49+
SCB_CleanDCache();
50+
SCB_EnableDCache();
51+
SCB_EnableICache();
4752
// Init clock
4853
BOARD_BootClockRUN();
4954
SystemCoreClockUpdate();
5055

5156
// Enable IOCON clock
5257
CLOCK_EnableClock(kCLOCK_Iomuxc);
5358

54-
// ------------- SDRAM ------------ //
59+
// SDRAM
5560
#if MICROPY_HW_SDRAM_AVAIL
5661
mimxrt_sdram_init();
5762
#endif
5863

5964
// 1ms tick timer
6065
SysTick_Config(SystemCoreClock / 1000);
6166

62-
// ------------- USB0 ------------- //
63-
// Clock
64-
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
65-
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
66-
67-
#ifdef USBPHY1
68-
USBPHY_Type *usb_phy = USBPHY1;
69-
#else
70-
USBPHY_Type *usb_phy = USBPHY;
71-
#endif
72-
73-
// Enable PHY support for Low speed device + LS via FS Hub
74-
usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
75-
76-
// Enable all power for normal operation
77-
usb_phy->PWD = 0;
78-
79-
// TX Timing
80-
uint32_t phytx = usb_phy->TX;
81-
phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
82-
phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
83-
usb_phy->TX = phytx;
84-
85-
// USB1
86-
// CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
87-
// CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
67+
// USB0
68+
usb_phy0_init(0b0111, 0b0110, 0b0110); // Configure nominal values for D_CAL and TXCAL45DP/DN
8869

8970
// ADC
9071
machine_adc_init();
@@ -99,6 +80,49 @@ void board_init(void) {
9980
#endif
10081
// RTC
10182
machine_rtc_start();
83+
84+
// OCRAM wait states (discarded, but code kept)
85+
#if 0
86+
MECC1->PIPE_ECC_EN =
87+
MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) |
88+
MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) |
89+
MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) |
90+
MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1);
91+
92+
MECC2->PIPE_ECC_EN =
93+
MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) |
94+
MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) |
95+
MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) |
96+
MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1);
97+
98+
FLEXRAM->FLEXRAM_CTRL =
99+
FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(1) |
100+
FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(1) |
101+
FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(1) |
102+
FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(1);
103+
#endif
104+
}
105+
106+
void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn) {
107+
#ifdef USBPHY1
108+
USBPHY_Type *usb_phy = USBPHY1;
109+
#else
110+
USBPHY_Type *usb_phy = USBPHY;
111+
#endif
112+
113+
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
114+
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ);
115+
116+
#if defined(MIMXRT117x_SERIES)
117+
usb_phy->TRIM_OVERRIDE_EN = USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(1) |
118+
USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(1) |
119+
USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(1) |
120+
USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(1) |
121+
USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(1); // Enable override for D_CAL and TXCAL45DP/DN
122+
#endif
123+
usb_phy->PWD = 0U; // Set all bits in PWD register to normal operation
124+
usb_phy->TX = ((usb_phy->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
125+
(USBPHY_TX_D_CAL(d_cal) | USBPHY_TX_TXCAL45DP(txcal45dp) | USBPHY_TX_TXCAL45DM(txcal45dn))); // Configure values for D_CAL and TXCAL45DP/DN
102126
}
103127

104128
void USB_OTG1_IRQHandler(void) {

‎ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h

+1
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@
5454
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx }
5555
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx }
5656
#define I2S_WM8960_RX_MODE (1)
57+
#define I2S_AUDIO_PLL_CLOCK (2U)
5758

5859
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
5960
{ \

‎ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h

+1
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@
5959
#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
6060
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
6161
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
62+
#define I2S_AUDIO_PLL_CLOCK (2U)
6263

6364
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
6465
{ \

‎ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h

+3-2
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@
7373
#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
7474
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
7575
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
76+
#define I2S_AUDIO_PLL_CLOCK (2U)
7677

7778
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
7879
{ \
@@ -158,8 +159,8 @@
158159
#define ENET_PHY_OPS phyksz8081_ops
159160

160161
// Etherner PIN definitions
161-
#define ENET_RESET_PIN pin_GPIO_AD_B0_04
162-
#define ENET_INT_PIN pin_GPIO_AD_B1_06
162+
#define ENET_RESET_PIN &pin_GPIO_AD_B0_04
163+
#define ENET_INT_PIN &pin_GPIO_AD_B1_06
163164

164165
#define IOMUX_TABLE_ENET \
165166
{ IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1, 0xB0E9u }, \

‎ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h

+3-2
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@
6262
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
6363
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
6464
#define I2S_WM8960_RX_MODE (1)
65+
#define I2S_AUDIO_PLL_CLOCK (2U)
6566

6667
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
6768
{ \
@@ -148,8 +149,8 @@
148149
#define ENET_PHY_OPS phyksz8081_ops
149150

150151
// Etherner PIN definitions
151-
#define ENET_RESET_PIN pin_GPIO_AD_B0_09
152-
#define ENET_INT_PIN pin_GPIO_AD_B0_10
152+
#define ENET_RESET_PIN &pin_GPIO_AD_B0_09
153+
#define ENET_INT_PIN &pin_GPIO_AD_B0_10
153154

154155
#define IOMUX_TABLE_ENET \
155156
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \

‎ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h

+3-2
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@
6262
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
6363
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
6464
#define I2S_WM8960_RX_MODE (1)
65+
#define I2S_AUDIO_PLL_CLOCK (2U)
6566

6667
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
6768
{ \
@@ -146,8 +147,8 @@
146147
#define ENET_PHY_OPS phyksz8081_ops
147148

148149
// Etherner PIN definitions
149-
#define ENET_RESET_PIN pin_GPIO_AD_B0_09
150-
#define ENET_INT_PIN pin_GPIO_AD_B0_10
150+
#define ENET_RESET_PIN &pin_GPIO_AD_B0_09
151+
#define ENET_INT_PIN &pin_GPIO_AD_B0_10
151152

152153
#define IOMUX_TABLE_ENET \
153154
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \

‎ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h

+3-2
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@
6262
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
6363
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
6464
#define I2S_WM8960_RX_MODE (1)
65+
#define I2S_AUDIO_PLL_CLOCK (2U)
6566

6667
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
6768
{ \
@@ -146,8 +147,8 @@
146147
#define ENET_PHY_OPS phyksz8081_ops
147148

148149
// Etherner PIN definitions
149-
#define ENET_RESET_PIN pin_GPIO_AD_B0_09
150-
#define ENET_INT_PIN pin_GPIO_AD_B0_10
150+
#define ENET_RESET_PIN &pin_GPIO_AD_B0_09
151+
#define ENET_INT_PIN &pin_GPIO_AD_B0_10
151152

152153
#define IOMUX_TABLE_ENET \
153154
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \

‎ports/mimxrt/boards/MIMXRT1170_EVK/board.json

+28
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
{
2+
"deploy": [
3+
"../deploy_mimxrt.md"
4+
],
5+
"docs": "",
6+
"features": [
7+
"Ethernet",
8+
"SDRAM",
9+
"MicroSD",
10+
"MicroUSB",
11+
"Microphone",
12+
"AudioCodec",
13+
"SPDIF",
14+
"CAN",
15+
"Camera",
16+
"SIM Socket",
17+
"OpenSDA",
18+
"JLink"
19+
],
20+
"images": [
21+
"IMX-RT1170-EVK-TOP.jpg"
22+
],
23+
"mcu": "mimxrt",
24+
"product": "MIMXRT1170_EVK",
25+
"thumbnail": "",
26+
"url": "https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK",
27+
"vendor": "NXP"
28+
}

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