Dataflow: Fixup some qldoc.

aschackmull · aschackmull · commit da34c0b3aceb · 2025-02-04T10:47:01.000+01:00
diff --git a/shared/dataflow/codeql/dataflow/internal/DataFlowImpl.qll b/shared/dataflow/codeql/dataflow/internal/DataFlowImpl.qll
@@ -169,7 +169,8 @@ module MakeImpl<LocationSig Location, InputSig<Location> Lang> {
   }
 
   /**
-   * Constructs a data flow computation given a full input configuration.
+   * Constructs a data flow computation given a full input configuration, and
+   * an initial stage 1 pruning.
    */
   module Impl<FullStateConfigSig Config, Stage1Output<Config::FlowState> Stage1> {
     private class FlowState = Config::FlowState;
diff --git a/shared/dataflow/codeql/dataflow/internal/DataFlowImplStage1.qll b/shared/dataflow/codeql/dataflow/internal/DataFlowImplStage1.qll
@@ -460,7 +460,6 @@ module MakeImplStage1<LocationSig Location, InputSig<Location> Lang> {
 
       private class Cc = boolean;
 
-      /* Begin: Stage 1 logic. */
       /**
        * Holds if `node` is reachable from a source.
        *
@@ -954,7 +953,6 @@ module MakeImplStage1<LocationSig Location, InputSig<Location> Lang> {
             callEdgeReturn(call, c, _, _, _, _)
           )
       }
-      /* End: Stage 1 logic. */
     }
 
     private module Stage1Common {

Original file line number	Diff line number	Diff line change
`@@ -169,7 +169,8 @@ module MakeImpl<LocationSig Location, InputSig<Location> Lang> {`
`169`	`169`	`}`
`170`	`170`
`171`	`171`	`/**`
`172`		`- * Constructs a data flow computation given a full input configuration.`
	`172`	`+ * Constructs a data flow computation given a full input configuration, and`
	`173`	`+ * an initial stage 1 pruning.`
`173`	`174`	`*/`
`174`	`175`	`module Impl<FullStateConfigSig Config, Stage1Output<Config::FlowState> Stage1> {`
`175`	`176`	`private class FlowState = Config::FlowState;`
Original file line number	Diff line number	Diff line change
`@@ -460,7 +460,6 @@ module MakeImplStage1<LocationSig Location, InputSig<Location> Lang> {`
`460`	`460`
`461`	`461`	`private class Cc = boolean;`
`462`	`462`
`463`		`- /* Begin: Stage 1 logic. */`
`464`	`463`	`/**`
`465`	`464`	* Holds if `node` is reachable from a source.
`466`	`465`	`*`
`@@ -954,7 +953,6 @@ module MakeImplStage1<LocationSig Location, InputSig<Location> Lang> {`
`954`	`953`	`callEdgeReturn(call, c, _, _, _, _)`
`955`	`954`	`)`
`956`	`955`	`}`
`957`		`- /* End: Stage 1 logic. */`
`958`	`956`	`}`
`959`	`957`
`960`	`958`	`private module Stage1Common {`