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fix double pull conflict
1 parent 08db413 commit 67bdcaa

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3 files changed

+20
-10
lines changed

3 files changed

+20
-10
lines changed

src/riscv/codegen.mbt

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -742,7 +742,10 @@ fn CodegenBlock::codegen(self : CodegenBlock) -> Unit {
742742
let reg_lhs = self.pull_val_i(lhs)
743743
// NOTE: whenever we pull 2 regs and both of them maybe tmp,
744744
// we replace the second tmp with target
745-
let reg_rhs = self.pull_val_i(rhs, reg_swap=reg)
745+
let reg_rhs = self.pull_val_i(
746+
rhs,
747+
reg_swap=if reg_lhs == reg_swap { reg } else { reg_swap },
748+
)
746749
match op {
747750
Add => [Add(reg, reg_lhs, reg_rhs)]
748751
Sub => [Sub(reg, reg_lhs, reg_rhs)]
@@ -756,7 +759,10 @@ fn CodegenBlock::codegen(self : CodegenBlock) -> Unit {
756759
bind,
757760
fn(reg) {
758761
let reg_lhs = self.pull_val_f(lhs)
759-
let reg_rhs = self.pull_val_f(rhs, freg_swap=reg)
762+
let reg_rhs = self.pull_val_f(
763+
rhs,
764+
freg_swap=if reg_lhs == freg_swap { reg } else { freg_swap },
765+
)
760766
match op {
761767
Add => [FaddD(reg, reg_lhs, reg_rhs)]
762768
Sub => [FsubD(reg, reg_lhs, reg_rhs)]
@@ -781,7 +787,10 @@ fn CodegenBlock::codegen(self : CodegenBlock) -> Unit {
781787
self.assign_i(
782788
bind,
783789
fn(reg) {
784-
let reg_rhs = self.pull_val_i(rhs, reg_swap=reg)
790+
let reg_rhs = self.pull_val_i(
791+
rhs,
792+
reg_swap=if reg_lhs == reg_swap { reg } else { reg_swap },
793+
)
785794
[Xor(reg_swap, reg_lhs, reg_rhs), Seqz(reg, reg_swap)]
786795
},
787796
)
@@ -804,7 +813,10 @@ fn CodegenBlock::codegen(self : CodegenBlock) -> Unit {
804813
bind,
805814
// HACK: we're using 32bits int so this won't overflow
806815
fn(reg) {
807-
let reg_rhs = self.pull_val_i(rhs, reg_swap=reg)
816+
let reg_rhs = self.pull_val_i(
817+
rhs,
818+
reg_swap=if reg_lhs == reg_swap { reg } else { reg_swap },
819+
)
808820
[
809821
Sub(reg, reg_lhs, reg_rhs),
810822
Addi(reg, reg, -1),

src/riscv/extern_stub.mbt

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@ fn collect_externals(cfg : @ssacfg.SsaCfg) -> @hashset.T[Var] {
1717
}
1818

1919
for item in cfg.blocks {
20-
//println("start of \{item.0}: \{out}")
2120
let (_, blk) = item
2221
for inst in blk.insts {
2322
match inst {
@@ -122,13 +121,13 @@ fn generate_stub(cfg : @ssacfg.SsaCfg) -> AssemblyFunction {
122121
body.append(
123122
[
124123
Label(stub_resolved),
125-
Comment("call the external function"),
124+
Comment("Call the external function"),
126125
Jalr(T6),
127-
Comment("A0 holds result, put continuation as 2nd arg"),
126+
Comment("Put continuation at \{kont_reg}"),
128127
Mv(kont_reg, S1),
129-
Comment("fetch continuation address"),
128+
Comment("Fetch continuation address"),
130129
Ld(T1, { base: S1, offset: 0 }),
131-
Comment("call continuation"),
130+
Comment("Call continuation"),
132131
Jr(T1),
133132
],
134133
)

src/riscv/reg_allocation.mbt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,6 @@ fn reg_allocate_on_fn(
3131
input : @ssacfg.SsaCfg,
3232
fn_label : Var
3333
) -> @hashmap.T[Var, RegRef] {
34-
//println("allocation for \{fn_label}")
3534

3635
// generate pre allocation
3736
let allocation_i : @hashmap.T[Var, Reg] = @hashmap.new()

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