@@ -24,114 +24,114 @@ const (
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//
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// The table is formatted for 8-space tabs.
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var progtable = [arm .ALAST ]obj.ProgInfo {
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- obj .ATYPE : {gc .Pseudo | gc .Skip , 0 , 0 , 0 },
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- obj .ATEXT : {gc .Pseudo , 0 , 0 , 0 },
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- obj .AFUNCDATA : {gc .Pseudo , 0 , 0 , 0 },
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- obj .APCDATA : {gc .Pseudo , 0 , 0 , 0 },
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- obj .AUNDEF : {gc .Break , 0 , 0 , 0 },
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- obj .AUSEFIELD : {gc .OK , 0 , 0 , 0 },
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- obj .ACHECKNIL : {gc .LeftRead , 0 , 0 , 0 },
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- obj .AVARDEF : {gc .Pseudo | gc .RightWrite , 0 , 0 , 0 },
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- obj .AVARKILL : {gc .Pseudo | gc .RightWrite , 0 , 0 , 0 },
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+ obj .ATYPE : {Flags : gc .Pseudo | gc .Skip },
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+ obj .ATEXT : {Flags : gc .Pseudo },
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+ obj .AFUNCDATA : {Flags : gc .Pseudo },
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+ obj .APCDATA : {Flags : gc .Pseudo },
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+ obj .AUNDEF : {Flags : gc .Break },
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+ obj .AUSEFIELD : {Flags : gc .OK },
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+ obj .ACHECKNIL : {Flags : gc .LeftRead },
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+ obj .AVARDEF : {Flags : gc .Pseudo | gc .RightWrite },
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+ obj .AVARKILL : {Flags : gc .Pseudo | gc .RightWrite },
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// NOP is an internal no-op that also stands
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// for USED and SET annotations, not the Intel opcode.
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- obj .ANOP : {gc .LeftRead | gc .RightWrite , 0 , 0 , 0 },
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+ obj .ANOP : {Flags : gc .LeftRead | gc .RightWrite },
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// Integer.
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- arm .AADC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AADD : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AAND : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ABIC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ACMN : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
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- arm .ACMP : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
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- arm .ADIVU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ADIV : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AEOR : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMODU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMOD : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMULALU : {gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr , 0 , 0 , 0 },
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- arm .AMULAL : {gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr , 0 , 0 , 0 },
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- arm .AMULA : {gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr , 0 , 0 , 0 },
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- arm .AMULU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMUL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMULL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMULLU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AMVN : {gc .SizeL | gc .LeftRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .AORR : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ARSB : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ARSC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ASBC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ASLL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ASRA : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ASRL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ASUB : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
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- arm .ATEQ : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
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- arm .ATST : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
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+ arm .AADC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AADD : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AAND : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ABIC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ACMN : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
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+ arm .ACMP : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
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+ arm .ADIVU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ADIV : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AEOR : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMODU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMOD : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMULALU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr },
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+ arm .AMULAL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr },
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+ arm .AMULA : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr },
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+ arm .AMULU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMUL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMULL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMULLU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .AMVN : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite },
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+ arm .AORR : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ARSB : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ARSC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ASBC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ASLL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ASRA : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ASRL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ASUB : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
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+ arm .ATEQ : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
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+ arm .ATST : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
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// Floating point.
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- arm .AADDD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .AADDF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .ACMPD : {gc .SizeD | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
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- arm .ACMPF : {gc .SizeF | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
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- arm .ADIVD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .ADIVF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .AMULD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .AMULF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .ASUBD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .ASUBF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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- arm .ASQRTD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
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+ arm .AADDD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
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+ arm .AADDF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
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+ arm .ACMPD : {Flags : gc .SizeD | gc .LeftRead | gc .RightRead },
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+ arm .ACMPF : {Flags : gc .SizeF | gc .LeftRead | gc .RightRead },
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+ arm .ADIVD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
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+ arm .ADIVF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
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+ arm .AMULD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
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+ arm .AMULF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
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+ arm .ASUBD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
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+ arm .ASUBF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
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+ arm .ASQRTD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
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// Conversions.
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- arm .AMOVWD : {gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVWF : {gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVDF : {gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVDW : {gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVFD : {gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVFW : {gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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+ arm .AMOVWD : {Flags : gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVWF : {Flags : gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVDF : {Flags : gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVDW : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVFD : {Flags : gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVFW : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv },
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// Moves.
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- arm .AMOVB : {gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
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- arm .AMOVD : {gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
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- arm .AMOVF : {gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
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- arm .AMOVH : {gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
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- arm .AMOVW : {gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
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+ arm .AMOVB : {Flags : gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Move },
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+ arm .AMOVD : {Flags : gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Move },
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+ arm .AMOVF : {Flags : gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Move },
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+ arm .AMOVH : {Flags : gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Move },
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+ arm .AMOVW : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Move },
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// In addtion, duffzero reads R0,R1 and writes R1. This fact is
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// encoded in peep.c
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- obj .ADUFFZERO : {gc .Call , 0 , 0 , 0 },
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+ obj .ADUFFZERO : {Flags : gc .Call },
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// In addtion, duffcopy reads R1,R2 and writes R0,R1,R2. This fact is
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// encoded in peep.c
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- obj .ADUFFCOPY : {gc .Call , 0 , 0 , 0 },
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+ obj .ADUFFCOPY : {Flags : gc .Call },
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// These should be split into the two different conversions instead
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// of overloading the one.
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- arm .AMOVBS : {gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVBU : {gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVHS : {gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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- arm .AMOVHU : {gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
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+ arm .AMOVBS : {Flags : gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVBU : {Flags : gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVHS : {Flags : gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv },
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+ arm .AMOVHU : {Flags : gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv },
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// Jumps.
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- arm .AB : {gc .Jump | gc .Break , 0 , 0 , 0 },
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- arm .ABL : {gc .Call , 0 , 0 , 0 },
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- arm .ABEQ : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABNE : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABCS : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABHS : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABCC : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABLO : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABMI : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABPL : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABVS : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABVC : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABHI : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABLS : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABGE : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABLT : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABGT : {gc .Cjmp , 0 , 0 , 0 },
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- arm .ABLE : {gc .Cjmp , 0 , 0 , 0 },
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- obj .ARET : {gc .Break , 0 , 0 , 0 },
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+ arm .AB : {Flags : gc .Jump | gc .Break },
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+ arm .ABL : {Flags : gc .Call },
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+ arm .ABEQ : {Flags : gc .Cjmp },
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+ arm .ABNE : {Flags : gc .Cjmp },
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+ arm .ABCS : {Flags : gc .Cjmp },
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+ arm .ABHS : {Flags : gc .Cjmp },
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+ arm .ABCC : {Flags : gc .Cjmp },
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+ arm .ABLO : {Flags : gc .Cjmp },
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+ arm .ABMI : {Flags : gc .Cjmp },
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+ arm .ABPL : {Flags : gc .Cjmp },
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+ arm .ABVS : {Flags : gc .Cjmp },
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+ arm .ABVC : {Flags : gc .Cjmp },
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+ arm .ABHI : {Flags : gc .Cjmp },
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+ arm .ABLS : {Flags : gc .Cjmp },
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+ arm .ABGE : {Flags : gc .Cjmp },
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+ arm .ABLT : {Flags : gc .Cjmp },
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+ arm .ABGT : {Flags : gc .Cjmp },
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+ arm .ABLE : {Flags : gc .Cjmp },
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+ obj .ARET : {Flags : gc .Break },
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}
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func proginfo (p * obj.Prog ) {
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