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1 |
| -// Copyright 2022 The Go Authors. All rights reserved. |
2 |
| -// Use of this source code is governed by a BSD-style |
3 |
| -// license that can be found in the LICENSE file. |
4 |
| -
|
5 |
| -// Prefer SARX/SHLX/SHRX instruction because it has less register restriction on the shift input. |
6 |
| -(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y) |
7 |
| -(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y) |
8 |
| -(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y) |
9 |
| -
|
10 |
| -// See comments in ARM64latelower.rules for why these are here. |
11 |
| -(MOVLQZX x) && zeroUpper32Bits(x,3) => x |
12 |
| -(MOVWQZX x) && zeroUpper48Bits(x,3) => x |
13 |
| -(MOVBQZX x) && zeroUpper56Bits(x,3) => x |
| 1 | +// Copyright 2022 The Go Authors. All rights reserved. |
| 2 | +// Use of this source code is governed by a BSD-style |
| 3 | +// license that can be found in the LICENSE file. |
| 4 | + |
| 5 | +// Prefer SARX/SHLX/SHRX instruction because it has less register restriction on the shift input. |
| 6 | +(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y) |
| 7 | +(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y) |
| 8 | +(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y) |
| 9 | + |
| 10 | +// See comments in ARM64latelower.rules for why these are here. |
| 11 | +(MOVLQZX x) && zeroUpper32Bits(x,3) => x |
| 12 | +(MOVWQZX x) && zeroUpper48Bits(x,3) => x |
| 13 | +(MOVBQZX x) && zeroUpper56Bits(x,3) => x |
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