[cleanup] Move all ice40 oriented code to contrib directory.

We were targeting small FPGAs in early experiments but our primary focus is ASIC and we can use open PDKs for that in OSS (e.g. ASAP7, SKY130). PiperOrigin-RevId: 610799670
google · Feb 27, 2024 · 97a2a67 · 97a2a67
1 parent e4d3071
commit 97a2a67
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diff --git a/xls/contrib/ice40/BUILD b/xls/contrib/ice40/BUILD
@@ -0,0 +1,213 @@
+# Copyright 2024 The XLS Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+package(
+    default_applicable_licenses = ["//:license"],
+    default_visibility = ["//xls:xls_internal"],
+    licenses = ["notice"],  # Apache 2.0
+)
+
+cc_library(
+    name = "wrap_io",
+    srcs = ["wrap_io.cc"],
+    hdrs = ["wrap_io.h"],
+    deps = [
+        ":io_strategy",
+        "//xls/codegen:finite_state_machine",
+        "//xls/codegen:module_signature",
+        "//xls/codegen:vast",
+        "//xls/common:math_util",
+        "//xls/common/status:ret_check",
+        "//xls/common/status:status_macros",
+        "//xls/ir:source_location",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+    ],
+)
+
+cc_test(
+    name = "wrap_io_test",
+    srcs = ["wrap_io_test.cc"],
+    data = glob(["testdata/wrap_io_test_*.vtxt"]),
+    deps = [
+        ":ice40_io_strategy",
+        ":null_io_strategy",
+        ":wrap_io",
+        "//xls/codegen:module_signature",
+        "//xls/codegen:vast",
+        "//xls/common:xls_gunit",
+        "//xls/common:xls_gunit_main",
+        "//xls/common/logging",
+        "//xls/common/status:matchers",
+        "//xls/ir:source_location",
+        "//xls/simulation:module_testbench",
+        "//xls/simulation:module_testbench_thread",
+        "//xls/simulation:verilog_test_base",
+    ],
+)
+
+cc_library(
+    name = "ice40_io_strategy",
+    srcs = ["ice40_io_strategy.cc"],
+    hdrs = ["ice40_io_strategy.h"],
+    data = ["//xls/contrib/ice40/uncore_rtl/ice40:iceprog_includes"],
+    deps = [
+        ":io_strategy",
+        "//xls/codegen:vast",
+        "//xls/common/file:filesystem",
+        "//xls/common/file:get_runfile_path",
+        "//xls/common/status:status_macros",
+        "//xls/tools:verilog_include",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+    ],
+)
+
+cc_binary(
+    name = "wrap_io_main",
+    srcs = ["wrap_io_main.cc"],
+    deps = [
+        ":ice40_io_strategy_registry",
+        ":io_strategy",
+        ":io_strategy_factory",
+        ":wrap_io",
+        "//xls/codegen:module_signature",
+        "//xls/common:exit_status",
+        "//xls/common:init_xls",
+        "//xls/common/file:filesystem",
+        "//xls/common/logging",
+        "@com_google_absl//absl/flags:flag",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+    ],
+)
+
+cc_library(
+    name = "ice40_io_strategy_registry",
+    srcs = ["ice40_io_strategy_registry.cc"],
+    deps = [
+        ":ice40_io_strategy",
+        ":io_strategy_factory",
+        "//xls/common:module_initializer",
+    ],
+    alwayslink = True,
+)
+
+cc_binary(
+    name = "drpc_main",
+    srcs = ["drpc_main.cc"],
+    deps = [
+        ":device_rpc_strategy",
+        ":device_rpc_strategy_factory",
+        ":ice40_device_rpc_strategy_registry",
+        "//xls/common:exit_status",
+        "//xls/common:init_xls",
+        "//xls/common/logging",
+        "//xls/ir:format_preference",
+        "//xls/ir:ir_parser",
+        "@com_google_absl//absl/flags:flag",
+        "@com_google_absl//absl/status:statusor",
+        "@com_google_absl//absl/types:span",
+    ],
+)
+
+cc_library(
+    name = "ice40_device_rpc_strategy",
+    srcs = ["ice40_device_rpc_strategy.cc"],
+    hdrs = ["ice40_device_rpc_strategy.h"],
+    deps = [
+        ":device_rpc_strategy",
+        "//xls/common:math_util",
+        "//xls/common:strerror",
+        "//xls/common/file:filesystem",
+        "//xls/common/logging",
+        "//xls/common/status:ret_check",
+        "//xls/common/status:status_macros",
+        "@com_google_absl//absl/status:statusor",
+        "@com_google_absl//absl/strings",
+        "@com_google_absl//absl/strings:str_format",
+    ],
+)
+
+cc_library(
+    name = "ice40_device_rpc_strategy_registry",
+    srcs = ["ice40_device_rpc_strategy_registry.cc"],
+    deps = [
+        ":device_rpc_strategy_factory",
+        ":ice40_device_rpc_strategy",
+        "//xls/common:module_initializer",
+    ],
+    alwayslink = True,
+)
+
+cc_library(
+    name = "null_io_strategy",
+    srcs = ["null_io_strategy.cc"],
+    hdrs = ["null_io_strategy.h"],
+    deps = [
+        ":io_strategy",
+        "//xls/codegen:vast",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+    ],
+)
+
+cc_library(
+    name = "device_rpc_strategy",
+    hdrs = ["device_rpc_strategy.h"],
+    deps = [
+        "//xls/ir:type",
+        "//xls/ir:value",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+        "@com_google_absl//absl/types:span",
+    ],
+)
+
+cc_library(
+    name = "device_rpc_strategy_factory",
+    srcs = ["device_rpc_strategy_factory.cc"],
+    hdrs = ["device_rpc_strategy_factory.h"],
+    deps = [
+        ":device_rpc_strategy",
+        "@com_google_absl//absl/base:no_destructor",
+        "@com_google_absl//absl/container:flat_hash_map",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+        "@com_google_absl//absl/strings:str_format",
+    ],
+)
+
+cc_library(
+    name = "io_strategy",
+    hdrs = ["io_strategy.h"],
+    deps = [
+        "//xls/codegen:vast",
+        "//xls/tools:verilog_include",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+    ],
+)
+
+cc_library(
+    name = "io_strategy_factory",
+    srcs = ["io_strategy_factory.cc"],
+    hdrs = ["io_strategy_factory.h"],
+    deps = [
+        ":io_strategy",
+        "@com_google_absl//absl/base:no_destructor",
+        "@com_google_absl//absl/container:flat_hash_map",
+        "@com_google_absl//absl/status:statusor",
+    ],
+)
diff --git a/xls/contrib/ice40/README.md b/xls/contrib/ice40/README.md
@@ -0,0 +1 @@
+Utilities for working with designs placed onto the ICE40 FPGA; e.g. via yosys.
diff --git a/xls/tools/device_rpc_strategy.h → xls/contrib/ice40/device_rpc_strategy.h b/xls/tools/device_rpc_strategy.h → xls/contrib/ice40/device_rpc_strategy.h
diff --git a/xls/tools/device_rpc_strategy_factory.cc → ...trib/ice40/device_rpc_strategy_factory.cc b/xls/tools/device_rpc_strategy_factory.cc → ...trib/ice40/device_rpc_strategy_factory.cc
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "xls/tools/device_rpc_strategy_factory.h"
+#include "xls/contrib/ice40/device_rpc_strategy_factory.h"
 
 #include <memory>
 #include <string_view>

diff --git a/xls/tools/device_rpc_strategy_factory.h → ...ntrib/ice40/device_rpc_strategy_factory.h b/xls/tools/device_rpc_strategy_factory.h → ...ntrib/ice40/device_rpc_strategy_factory.h
@@ -24,7 +24,7 @@
 #include "absl/base/no_destructor.h"
 #include "absl/container/flat_hash_map.h"
 #include "absl/status/statusor.h"
-#include "xls/tools/device_rpc_strategy.h"
+#include "xls/contrib/ice40/device_rpc_strategy.h"
 
 namespace xls {
 

diff --git a/xls/tools/drpc_main.cc → xls/contrib/ice40/drpc_main.cc b/xls/tools/drpc_main.cc → xls/contrib/ice40/drpc_main.cc
@@ -32,10 +32,10 @@
 #include "xls/common/exit_status.h"
 #include "xls/common/init_xls.h"
 #include "xls/common/logging/logging.h"
+#include "xls/contrib/ice40/device_rpc_strategy.h"
+#include "xls/contrib/ice40/device_rpc_strategy_factory.h"
 #include "xls/ir/format_preference.h"
 #include "xls/ir/ir_parser.h"
-#include "xls/tools/device_rpc_strategy.h"
-#include "xls/tools/device_rpc_strategy_factory.h"
 
 ABSL_FLAG(std::string, target_device, "",
           "Target (category of) device for DRPC targeting; e.g. ice40.");

diff --git a/xls/tools/ice40_device_rpc_strategy.cc → ...ontrib/ice40/ice40_device_rpc_strategy.cc b/xls/tools/ice40_device_rpc_strategy.cc → ...ontrib/ice40/ice40_device_rpc_strategy.cc
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "xls/tools/ice40_device_rpc_strategy.h"
+#include "xls/contrib/ice40/ice40_device_rpc_strategy.h"
 
 #include <fcntl.h>
 #include <sys/stat.h>

diff --git a/xls/tools/ice40_device_rpc_strategy.h → ...contrib/ice40/ice40_device_rpc_strategy.h b/xls/tools/ice40_device_rpc_strategy.h → ...contrib/ice40/ice40_device_rpc_strategy.h
@@ -18,7 +18,7 @@
 #include <optional>
 
 #include "absl/status/statusor.h"
-#include "xls/tools/device_rpc_strategy.h"
+#include "xls/contrib/ice40/device_rpc_strategy.h"
 
 namespace xls {
 

diff --git a/...ols/ice40_device_rpc_strategy_registry.cc → ...e40/ice40_device_rpc_strategy_registry.cc b/...ols/ice40_device_rpc_strategy_registry.cc → ...e40/ice40_device_rpc_strategy_registry.cc
@@ -13,8 +13,8 @@
 // limitations under the License.
 
 #include "xls/common/module_initializer.h"
-#include "xls/tools/device_rpc_strategy_factory.h"
-#include "xls/tools/ice40_device_rpc_strategy.h"
+#include "xls/contrib/ice40/device_rpc_strategy_factory.h"
+#include "xls/contrib/ice40/ice40_device_rpc_strategy.h"
 
 XLS_REGISTER_MODULE_INITIALIZER(xls_tools_ice40_device_rpc_strategy_registry, {
   xls::DeviceRpcStrategyFactory::GetSingleton().Add("ice40", []() {

diff --git a/xls/tools/ice40_io_strategy.cc → xls/contrib/ice40/ice40_io_strategy.cc b/xls/tools/ice40_io_strategy.cc → xls/contrib/ice40/ice40_io_strategy.cc
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "xls/tools/ice40_io_strategy.h"
+#include "xls/contrib/ice40/ice40_io_strategy.h"
 
 #include <filesystem>
 #include <utility>

diff --git a/xls/tools/ice40_io_strategy.h → xls/contrib/ice40/ice40_io_strategy.h b/xls/tools/ice40_io_strategy.h → xls/contrib/ice40/ice40_io_strategy.h
@@ -20,7 +20,8 @@
 #include "absl/status/status.h"
 #include "absl/status/statusor.h"
 #include "xls/codegen/vast.h"
-#include "xls/tools/wrap_io.h"
+#include "xls/contrib/ice40/io_strategy.h"
+#include "xls/tools/verilog_include.h"
 
 namespace xls {
 namespace verilog {
@@ -40,9 +41,8 @@ class Ice40IoStrategy : public IOStrategy {
  private:
   // The files tick-included by the IO strategy.
   constexpr static const char* kIncludes[] = {
-      "xls/uncore_rtl/ice40/uart_receiver.v",
-      "xls/uncore_rtl/ice40/uart_transmitter.v"
-  };
+      "xls/contrib/ice40/uncore_rtl/ice40/uart_receiver.v",
+      "xls/contrib/ice40/uncore_rtl/ice40/uart_transmitter.v"};
 
   VerilogFile* f_;
 

diff --git a/xls/tools/ice40_io_strategy_registry.cc → ...ntrib/ice40/ice40_io_strategy_registry.cc b/xls/tools/ice40_io_strategy_registry.cc → ...ntrib/ice40/ice40_io_strategy_registry.cc
@@ -13,8 +13,8 @@
 // limitations under the License.
 
 #include "xls/common/module_initializer.h"
-#include "xls/tools/ice40_io_strategy.h"
-#include "xls/tools/io_strategy_factory.h"
+#include "xls/contrib/ice40/ice40_io_strategy.h"
+#include "xls/contrib/ice40/io_strategy_factory.h"
 
 XLS_REGISTER_MODULE_INITIALIZER(xls_tools_ice40_strategy_registry, {
   xls::verilog::IOStrategyFactory::GetSingleton().Add(

diff --git a/xls/tools/io_strategy.h → xls/contrib/ice40/io_strategy.h b/xls/tools/io_strategy.h → xls/contrib/ice40/io_strategy.h
diff --git a/xls/tools/io_strategy_factory.cc → xls/contrib/ice40/io_strategy_factory.cc b/xls/tools/io_strategy_factory.cc → xls/contrib/ice40/io_strategy_factory.cc
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "xls/tools/io_strategy_factory.h"
+#include "xls/contrib/ice40/io_strategy_factory.h"
 
 #include <memory>
 #include <string_view>

diff --git a/xls/tools/io_strategy_factory.h → xls/contrib/ice40/io_strategy_factory.h b/xls/tools/io_strategy_factory.h → xls/contrib/ice40/io_strategy_factory.h
@@ -24,7 +24,7 @@
 #include "absl/base/no_destructor.h"
 #include "absl/container/flat_hash_map.h"
 #include "absl/status/statusor.h"
-#include "xls/tools/io_strategy.h"
+#include "xls/contrib/ice40/io_strategy.h"
 
 namespace xls {
 namespace verilog {

diff --git a/xls/tools/null_io_strategy.cc → xls/contrib/ice40/null_io_strategy.cc b/xls/tools/null_io_strategy.cc → xls/contrib/ice40/null_io_strategy.cc
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "xls/tools/null_io_strategy.h"
+#include "xls/contrib/ice40/null_io_strategy.h"
 
 namespace xls {
 namespace verilog {

diff --git a/xls/tools/null_io_strategy.h → xls/contrib/ice40/null_io_strategy.h b/xls/tools/null_io_strategy.h → xls/contrib/ice40/null_io_strategy.h
@@ -20,7 +20,7 @@
 #include "absl/status/status.h"
 #include "absl/status/statusor.h"
 #include "xls/codegen/vast.h"
-#include "xls/tools/io_strategy.h"
+#include "xls/contrib/ice40/io_strategy.h"
 
 namespace xls {
 namespace verilog {

diff --git a/.../wrap_io_test_Ice40WrapIOIdentity32b.vtxt → .../wrap_io_test_Ice40WrapIOIdentity32b.vtxt b/.../wrap_io_test_Ice40WrapIOIdentity32b.vtxt → .../wrap_io_test_Ice40WrapIOIdentity32b.vtxt
@@ -4,8 +4,8 @@ module device_to_wrap(
 );
   assign out = in;
 endmodule
-`include "xls/uncore_rtl/ice40/uart_receiver.v"
-`include "xls/uncore_rtl/ice40/uart_transmitter.v"
+`include "xls/contrib/ice40/uncore_rtl/ice40/uart_receiver.v"
+`include "xls/contrib/ice40/uncore_rtl/ice40/uart_transmitter.v"
 module input_resetter(
   input wire clk,
   input wire [7:0] byte_in,
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		Utilities for working with designs placed onto the ICE40 FPGA; e.g. via yosys.