Confuse Markdown parsers less by not overdoing indentation.

PiperOrigin-RevId: 703053684

Author: hzeller

README.md

@@ -199,97 +199,96 @@ purpose, and correspond to the components in this XLS stack diagram:
     [mkdocs](https://google.github.io/xls/contributing/#rendering-documentation).
 *   [`xls`](https://github.com/google/xls/tree/main/xls): Project-named
     subdirectory within the repository, in common Bazel-project style.
-
-    *   [`build`](https://github.com/google/xls/tree/main/xls/BUILD): Build
-        macros that create XLS artifacts; e.g. convert DSL to IR, create test
-        targets for DSL code, etc.
-    *   [`codegen`](https://github.com/google/xls/tree/main/xls/codegen):
-        Verilog AST (VAST) support to generate Verilog/SystemVerilog operations
-        and FSMs. VAST is built up by components we call *generators* (e.g.
-        PipelineGenerator, SequentialGenerator for FSMs) in the translation from
-        XLS IR.
-    *   [`common`](https://github.com/google/xls/tree/main/xls/common): "base"
-        functionality that layers on top of standard library usage. Generally we
-        use [Abseil](https://abseil.io) versions of base constructs wherever
-        possible.
-    *   [`contrib/xlscc`](https://github.com/google/xls/tree/main/xls/contrib/xlscc):
-        Experimental C++ syntax support that targets XLS IR (alternative path to
-        DSLX) developed by a sister team at Google, sharing the same open source
-        / testing flow as the rest of the XLS project. May be of particular
-        interest for teams with existing C++ HLS code bases.
-    *   [`data_structures`](https://github.com/google/xls/tree/main/xls/data_structures):
-        Generic data structures used in XLS that augment standard libraries;
-        e.g. BDDs, union find, min cut, etc.
-    *   [`delay_model`](https://github.com/google/xls/tree/main/xls/estimators/delay_model):
-        Functionality to characterize, describe, and interpolate data delay for
-        XLS IR operations on a target backend process. Already-characterized
-        descriptions are placed in `xls/estimators/delay_model/models` and can
-        be referred to via command line flags.
-    *   [`dslx`](https://github.com/google/xls/tree/main/xls/dslx): A DSL
-        (called "DSLX") that mimics Rust, while being an immutable
-        expression-language dataflow DSL with hardware-oriented features; e.g.
-        arbitrary bitwidths, entirely fixed size objects, fully analyzeable call
-        graph. XLS team has found dataflow DSLs are a good fit to describe
-        hardware as compared to languages designed assume von Neumann style
-        computation.
-    *   [`fuzzer`](https://github.com/google/xls/tree/main/xls/fuzzer): A
-        whole-stack multiprocess fuzzer that generates programs at the DSL level
-        and cross-compares different execution engines (DSL interpreter, IR
-        interpreter, IR JIT, code-generated-Verilog simulator). Designed so that
-        it can easily be run on different nodes in a cluster simultaneously and
-        accumulate shared findings.
-    *   [`examples`](https://github.com/google/xls/tree/main/xls/examples):
-        Example computations that are tested and executable through the XLS
-        stack.
-    *   [`experimental`](https://github.com/google/xls/tree/main/xls/experimental):
-        Artifacts captured from experimental explorations.
-    *   [`interpreter`](https://github.com/google/xls/tree/main/xls/interpreter):
-        Interpreter for XLS IR - useful for debugging and exploration. For cases
-        needing throughput, consider using the JIT (below).
-    *   [`ir`](https://github.com/google/xls/tree/main/xls/ir): XLS IR
-        definition, text parser/formatter, and facilities for abstract
-        evaluation.
-    *   [`jit`](https://github.com/google/xls/tree/main/xls/jit): LLVM-based JIT
-        for XLS IR. Enables native-speed execution of DSLX and XLS IR programs.
-    *   [`modules`](https://github.com/google/xls/tree/main/xls/modules):
-        Hardware building block DSLX "libraries" (outside the DSLX standard
-        library) that may be easily reused or instantiated in a broader design.
-    *   [`netlist`](https://github.com/google/xls/tree/main/xls/netlist):
-        Libraries that parse/analyze/interpret netlist-level descriptions, as
-        are generally given in simple structural Verilog with an associated cell
-        library.
-    *   [`passes`](https://github.com/google/xls/tree/main/xls/passes): Passes
-        that run on the XLS IR as part of optimization, before scheduling / code
-        generation.
-    *   [`scheduling`](https://github.com/google/xls/tree/main/xls/scheduling):
-        Scheduling algorithms, determine when operations execute (e.g. which
-        pipeline stage) in a clocked design.
-    *   [`simulation`](https://github.com/google/xls/tree/main/xls/simulation):
-        Code that wraps Verilog simulators and generates Verilog testbenches for
-        XLS computations. [iverilog](https://github.com/steveicarus/iverilog) is
-        currently used to simulate as it supports non-synthesizable testbench
-        constructs.
-    *   [`solvers`](https://github.com/google/xls/tree/main/xls/solvers):
-        Converters from XLS IR into SMT solver input, such that formal proofs
-        can be run on XLS computations; e.g. Logical Equalence Checks between
-        XLS IR and a netlist description. [Z3](https://github.com/Z3Prover/z3)
-        is used as the solver engine.
-    *   [`synthesis`](https://github.com/google/xls/tree/main/xls/synthesis):
-        Interface that wraps backend synthesis flows, such that tools can be
-        retargeted e.g. between ASIC and FPGA flows.
-    *   [`tests`](https://github.com/google/xls/tree/main/xls/tests):
-        Integration tests that span various top-level components of the XLS
-        project.
-    *   [`tools`](https://github.com/google/xls/tree/main/xls/tools):
-        [Many tools](https://google.github.io/xls/tools/) that work with the XLS
-        system and its libraries in a decomposed way via command line
-        interfaces.
-    *   [`uncore_rtl`](https://github.com/google/xls/tree/main/xls/uncore_rtl):
-        Helper RTL that interfaces XLS-generated blocks with device top-level
-        for e.g. FPGA experiments.
-    *   [`visualization`](https://github.com/google/xls/tree/main/xls/visualization):
-        Visualization tools to inspect the XLS compiler/system interactively.
-        See [IR visualization](https://google.github.io/xls/ir_visualization/).
+  *   [`build`](https://github.com/google/xls/tree/main/xls/BUILD): Build
+      macros that create XLS artifacts; e.g. convert DSL to IR, create test
+      targets for DSL code, etc.
+  *   [`codegen`](https://github.com/google/xls/tree/main/xls/codegen):
+      Verilog AST (VAST) support to generate Verilog/SystemVerilog operations
+      and FSMs. VAST is built up by components we call *generators* (e.g.
+      PipelineGenerator, SequentialGenerator for FSMs) in the translation from
+      XLS IR.
+  *   [`common`](https://github.com/google/xls/tree/main/xls/common): "base"
+      functionality that layers on top of standard library usage. Generally we
+      use [Abseil](https://abseil.io) versions of base constructs wherever
+      possible.
+  *   [`contrib/xlscc`](https://github.com/google/xls/tree/main/xls/contrib/xlscc):
+      Experimental C++ syntax support that targets XLS IR (alternative path to
+      DSLX) developed by a sister team at Google, sharing the same open source
+      / testing flow as the rest of the XLS project. May be of particular
+      interest for teams with existing C++ HLS code bases.
+  *   [`data_structures`](https://github.com/google/xls/tree/main/xls/data_structures):
+      Generic data structures used in XLS that augment standard libraries;
+      e.g. BDDs, union find, min cut, etc.
+  *   [`delay_model`](https://github.com/google/xls/tree/main/xls/estimators/delay_model):
+      Functionality to characterize, describe, and interpolate data delay for
+      XLS IR operations on a target backend process. Already-characterized
+      descriptions are placed in `xls/estimators/delay_model/models` and can
+      be referred to via command line flags.
+  *   [`dslx`](https://github.com/google/xls/tree/main/xls/dslx): A DSL
+      (called "DSLX") that mimics Rust, while being an immutable
+      expression-language dataflow DSL with hardware-oriented features; e.g.
+      arbitrary bitwidths, entirely fixed size objects, fully analyzeable call
+      graph. XLS team has found dataflow DSLs are a good fit to describe
+      hardware as compared to languages designed assume von Neumann style
+      computation.
+  *   [`fuzzer`](https://github.com/google/xls/tree/main/xls/fuzzer): A
+      whole-stack multiprocess fuzzer that generates programs at the DSL level
+      and cross-compares different execution engines (DSL interpreter, IR
+      interpreter, IR JIT, code-generated-Verilog simulator). Designed so that
+      it can easily be run on different nodes in a cluster simultaneously and
+      accumulate shared findings.
+  *   [`examples`](https://github.com/google/xls/tree/main/xls/examples):
+      Example computations that are tested and executable through the XLS
+      stack.
+  *   [`experimental`](https://github.com/google/xls/tree/main/xls/experimental):
+      Artifacts captured from experimental explorations.
+  *   [`interpreter`](https://github.com/google/xls/tree/main/xls/interpreter):
+      Interpreter for XLS IR - useful for debugging and exploration. For cases
+      needing throughput, consider using the JIT (below).
+  *   [`ir`](https://github.com/google/xls/tree/main/xls/ir): XLS IR
+      definition, text parser/formatter, and facilities for abstract
+      evaluation.
+  *   [`jit`](https://github.com/google/xls/tree/main/xls/jit): LLVM-based JIT
+      for XLS IR. Enables native-speed execution of DSLX and XLS IR programs.
+  *   [`modules`](https://github.com/google/xls/tree/main/xls/modules):
+      Hardware building block DSLX "libraries" (outside the DSLX standard
+      library) that may be easily reused or instantiated in a broader design.
+  *   [`netlist`](https://github.com/google/xls/tree/main/xls/netlist):
+      Libraries that parse/analyze/interpret netlist-level descriptions, as
+      are generally given in simple structural Verilog with an associated cell
+      library.
+  *   [`passes`](https://github.com/google/xls/tree/main/xls/passes): Passes
+      that run on the XLS IR as part of optimization, before scheduling / code
+      generation.
+  *   [`scheduling`](https://github.com/google/xls/tree/main/xls/scheduling):
+      Scheduling algorithms, determine when operations execute (e.g. which
+      pipeline stage) in a clocked design.
+  *   [`simulation`](https://github.com/google/xls/tree/main/xls/simulation):
+      Code that wraps Verilog simulators and generates Verilog testbenches for
+      XLS computations. [iverilog](https://github.com/steveicarus/iverilog) is
+      currently used to simulate as it supports non-synthesizable testbench
+      constructs.
+  *   [`solvers`](https://github.com/google/xls/tree/main/xls/solvers):
+      Converters from XLS IR into SMT solver input, such that formal proofs
+      can be run on XLS computations; e.g. Logical Equalence Checks between
+      XLS IR and a netlist description. [Z3](https://github.com/Z3Prover/z3)
+      is used as the solver engine.
+  *   [`synthesis`](https://github.com/google/xls/tree/main/xls/synthesis):
+      Interface that wraps backend synthesis flows, such that tools can be
+      retargeted e.g. between ASIC and FPGA flows.
+  *   [`tests`](https://github.com/google/xls/tree/main/xls/tests):
+      Integration tests that span various top-level components of the XLS
+      project.
+  *   [`tools`](https://github.com/google/xls/tree/main/xls/tools):
+      [Many tools](https://google.github.io/xls/tools/) that work with the XLS
+      system and its libraries in a decomposed way via command line
+      interfaces.
+  *   [`uncore_rtl`](https://github.com/google/xls/tree/main/xls/uncore_rtl):
+      Helper RTL that interfaces XLS-generated blocks with device top-level
+      for e.g. FPGA experiments.
+  *   [`visualization`](https://github.com/google/xls/tree/main/xls/visualization):
+      Visualization tools to inspect the XLS compiler/system interactively.
+      See [IR visualization](https://google.github.io/xls/ir_visualization/).
 
 ## Community