[enhancement] Enable converting DSLX tests to SystemVerilog testbenches

[rw1nkler]

What's hard to do? (limit 100 words)

DSLX allows writing tests by marking functions and procs with #[test] and #[test_proc] attributes. These tests run only in the DSLX interpreter and are useful for functional checking. However, most of them cannot be easily converted to IR or Verilog, since they may rely on constructs such as multiple sends on the same channel or other features that cannot be lowered to IR. This makes it difficult to run the same tests on the generated Verilog design to verify correct behavior and measure performance.

Current best alternative workaround (limit 100 words)

One can work on lowering the created test to IR, which for some of them may be tedious. However sometimes, the easiest option is just to write SystemVerilog testbenches manually. This usually means repeating the same test logic and data that already exist in DSLX. It takes time, is error-prone, and makes it easy for the two versions to get out of sync when the design changes.

Your view of the "best case XLS enhancement" (limit 100 words)

It would be useful to have a tool that automatically generates Verilog testbenches from DSLX tests. The tool could take #[test] and #[test_proc] functions and produce Verilog simulation files that apply the same inputs and check the same outputs.

For the testbench generation the backend can make use of non-synthesizable statements to better reflect the original DSLX code and making both tests more similar to each other.

One challenge is that DSLX tests do not include timing information, so the generated testbench would lack explicit cycle-accurate behavior. This could be addressed by adding simple annotations to express timing directly in the test, for example:

let tok = send(tok, channel_s, value) @ cycle(2)

Alternatively, a cocotb-like approach could be used, where timing is specified through additional operations:

let tok = send(tok, channel_s, value)
wait cycles(2)

Those additional statements may be skipped in the normal DSLX interpreter execution.