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lbmengalistair23
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target/riscv: Generate the GDB XML file for CSR registers dynamically
At present QEMU RISC-V uses a hardcoded XML to report the feature "org.gnu.gdb.riscv.csr" [1]. There are two major issues with the approach being used currently: - The XML does not specify the "regnum" field of a CSR entry, hence consecutive numbers are used by the remote GDB client to access CSRs. In QEMU we have to maintain a map table to convert the GDB number to the hardware number which is error prone. - The XML contains some CSRs that QEMU does not implement at all, which causes an "E14" response sent to remote GDB client. Change to generate the CSR register list dynamically, based on the availability presented in the CSR function table. This new approach will reflect a correct list of CSRs that QEMU actually implements. [1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-id: [email protected] Signed-off-by: Alistair Francis <[email protected]>
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target/riscv/cpu.c

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@@ -569,6 +569,17 @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
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}
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}
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static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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if (strcmp(xmlname, "riscv-csr.xml") == 0) {
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return cpu->dyn_csr_xml;
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}
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return NULL;
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}
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static void riscv_cpu_class_init(ObjectClass *c, void *data)
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{
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RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -605,6 +616,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
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cc->vmsd = &vmstate_riscv_cpu;
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#endif
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cc->gdb_arch_name = riscv_gdb_arch_name;
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cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
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#ifdef CONFIG_TCG
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cc->tcg_initialize = riscv_translate_init;
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cc->tlb_fill = riscv_cpu_tlb_fill;

target/riscv/cpu.h

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@@ -272,6 +272,8 @@ struct RISCVCPU {
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CPUNegativeOffsetState neg;
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CPURISCVState env;
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char *dyn_csr_xml;
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/* Configuration Settings */
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struct {
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bool ext_i;

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