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Copy pathbitmain-asic-drv.c
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bitmain-asic-drv.c
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/*
* Bitmain asic driver
*
* Copyright (C) 2007-2008 Gabor Juhos <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* ---------------------------------------------------------------------------
*
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>
#include <linux/mutex.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/jiffies.h>
#include <linux/ratelimit.h>
#include <linux/timer.h>
#include <linux/timex.h>
#include <linux/rtc.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/uaccess.h>
//#include <asm/mach-ath79/ar71xx_regs.h>
//#include <asm/mach-ath79/ath79.h>
//#include <asm/mach-ath79/irq.h>
#include "spi.h"
#include "bitmain-asic.h"
#include "sha2.h"
#include "fpga.h"
bool fpga_ret_prnt = false;
bool rx_st_prnt = false;
int check_state = 10;
module_param(fpga_ret_prnt,bool,S_IRUGO);
module_param(rx_st_prnt,bool,S_IRUGO);
unsigned int hardware_version = 0;
static unsigned long Prnt_time_out = 0;
unsigned int GREEN, RED;
static void Prnt(unsigned long data);
static bool fan_custom = false;
static uint8_t custom_fan = 0;
void ChangePWM(BT_AS_INFO dev, unsigned int pwm_percent);
#define DRV_NAME "bitmain-asic"
#define DRV_DESC "Bitmain asic driver"
#define DRV_VERSION "0.1.1"
#define PRNT_TIMER_EN 1
#define CHAIN_POWER_TIME_INTERAL 5
#define TIMER_NUM 2
#define TIMER_INTERRUPT (15 + TIMER_NUM)
#define RESET_BASE (0x18000000 + 0x00060000)
#define RESET_SIZE 0x100
#define GENERAL_TIMER (0x94+8*(TIMER_NUM-1))
#define GENERAL_TIMER_RELOAD (GENERAL_TIMER + 0x04)
//AHB 时钟200 MHz
#define TIME_40MS (40*200*1000)
//extern struct file_operations *bitmain_fops_p;
// Add by Fazio, state machine
enum TEMP_STATE{TEMP_NORMAL,TEMP_WARN,TEMP_OUT_STATE};
enum FAN_STATE{FAN_NORMAL,FAN_WARN,FAN_ERROR};
enum FIFO_STATE{FIFO_NORMAL,ALLFIFO_EMPTY};
enum CHAIN_STATE{CHAIN_NO_NONCE_TO,CHAIN_ERROR,CHAIN_NORMAL};
typedef void (* actiontype)(BT_AS_INFO);
static bool if_temp_out_stop = false;
unsigned int gNonce_num = 0, gNonce_Err = 0, gNonce_miss = 0, gDiff_nonce_num = 0, gSubmit_nonce_num = 0;
uint32_t last_read_nonce_jiffies = 0;
uint16_t gTotal_asic_num = 0;
uint8_t gChain_Asic_Check_bit[CHAIN_SIZE] = {0};
uint8_t gChain_Asic_Interval[CHAIN_SIZE] = {0};
uint8_t gChain_Asic_num[CHAIN_SIZE] = {0};
uint32_t gChain_Asic_status[CHAIN_SIZE][256/32];
uint32_t gAsic_cnt[CHAIN_SIZE][256];
uint32_t Chain_nonce_nu[CHAIN_SIZE] = {0};
uint32_t Chain_nonce_nu_last[CHAIN_SIZE] = {0};
static unsigned char config_fpga = 0;
#if PRNT_TIMER_EN
static struct timer_list prnt_timer;
#endif
#if 0
typedef struct __BT_AS_info
{
spinlock_t lock;
struct mutex result_lock;
void __iomem *virt_addr;
unsigned irq;
struct workqueue_struct *usb_wq;
struct work_struct usb_sdata_work;
struct delayed_work usb_rdata_work;
ASIC_TASK_P task_buffer;
unsigned char task_last_num;
unsigned char task_current_num;
unsigned int task_buffer_size;
unsigned int task_buffer_wr;
unsigned int task_buffer_rd;
bool task_buffer_full;
bool usb_opened;
bool get_status;
ASIC_CONFIGURE asic_configure;
struct BITMAIN_STATUS_DATA asic_status_data;
}*BT_AS_INFO;
#endif
struct __BT_AS_info bitmain_asic_dev;
struct inode bitmain_inode;
struct file bitmain_file;
static unsigned long bitmain_is_open;
static void *gpio1_vaddr;
void *gpio0_vaddr;
uint8_t asic_return_bytes = 5;
// --------------------------------------------------------------
// CRC16 check table
// --------------------------------------------------------------
const uint8_t chCRCHTalbe[] = // CRC high byte table
{
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40
};
const uint8_t chCRCLTalbe[] = // CRC low byte table
{
0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
0x41, 0x81, 0x80, 0x40
};
uint16_t CRC16(const uint8_t* p_data, uint16_t w_len)
{
uint8_t chCRCHi = 0xFF; // CRC high byte initialize
uint8_t chCRCLo = 0xFF; // CRC low byte initialize
uint16_t wIndex = 0; // CRC cycling index
while (w_len--) {
wIndex = chCRCLo ^ *p_data++;
chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
chCRCHi = chCRCLTalbe[wIndex];
}
return ((chCRCHi << 8) | chCRCLo);
}
int cmd_check(uint8_t *data)//OK 1; failure 0
{
BITMAIN_TASK_P bt = (BITMAIN_TASK_P)data;
uint16_t r_crc = 0;
uint16_t crc = bt->crc;
uint16_t length = 0;
if(bt->token_type == BM_TX_TASK)
{
#if HAVE_NUM
uint16_t len = 4 + bt->work_num*sizeof(struct ASIC_TASK);
#else
uint16_t len = le16_to_cpu(bt->length)+ 4 - 2;
#endif
crc = data[len] | (data[len+1]<<8);
length = le16_to_cpu(bt->length) + 2;
}
else if(bt->token_type == BM_TX_CONF)
{
BITMAIN_CONFIGURE_P btc = (BITMAIN_CONFIGURE_P)data;
length = btc->length+2;
crc = cpu_to_le16(btc->crc);
}
else if(bt->token_type == BM_GET_STATUS)
{
BITMAIN_GET_STATUS_P bgs = (BITMAIN_GET_STATUS_P)data;
length = bgs->length+2;
crc = cpu_to_le16(bgs->crc);
}
else
{
printk_ratelimited("Tx token err {%#x}\n", bt->token_type);
return 0;
}
if(crc == (r_crc=CRC16(data, length)))//length 去除了type和length
{
//rintf("OK: crc{%#x}r_crc{%#x}\n", crc, r_crc);
return 1;
}
else
{
printk_ratelimited("Err:token{%#x} crc{%#x}r_crc{%#x}len{%#x}\n",
bt->token_type, crc, r_crc,length);
if(bt->token_type == BM_TX_TASK)
{
#if HAVE_NUM
printk_ratelimited("work_num {%d}\n", bt->work_num);
#else
printk_ratelimited("work_num {%d}\n", (le16_to_cpu(bt->length) - 6)/sizeof(struct ASIC_TASK));
#endif
}
return 0;
}
}
inline void increase_variable_rehead_U32(uint32_t *num, uint32_t all_size)
{
*num = *num + 1;
if (*num >= all_size)
*num = 0;
return;
}
extern void dump_hex(uint8_t *data, uint16_t len)
{
uint16_t i;
for(i = 0; i < len; i++)
{
if(0 == (i%16))
printk_ratelimited("\n0x%04x: ", i);
printk_ratelimited("0x%02x ", data[i]);
}
printk_ratelimited("\n");
}
static __inline void flip80(void *dest_p, const void *src_p)
{
uint32_t *dest = dest_p;
const uint32_t *src = src_p;
int i;
for (i = 0; i < 20; i++)
dest[i] = swab32(src[i]);
}
static __inline void flip32(void *dest_p, const void *src_p)
{
uint32_t *dest = dest_p;
const uint32_t *src = src_p;
int i;
for (i = 0; i < 8; i++)
dest[i] = swab32(src[i]);
}
static __inline void flip_swab(void *dest_p, const void *src_p, unsigned int length)
{
uint32_t *dest = dest_p;
const uint32_t *src = src_p;
int i;
for (i = 0; i < length/4; i++)
dest[i] = swab32(src[i]);
}
#if 1
const char g_full_data[] = { "0000000258007a06037bb0c899e253afc369f10c9e7762a8aa73d33b00000034000000009d5146878f7fda9f7f7f76f1c1aa6751f679e3aff3f722b2030b0eac"
"814f5d975201f3ba1972dbf2"
"ae319135"
"000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000"
};
#if 0
//midstate data向芯片发送不需要反
const char g_midstate[] = {"2e26c4440504a801393d373204e87cc02828ba7fd6f191add1b0ff01a9302ac0"};//需要反序 (现在左侧为高位，右侧为低位 )
const char g_data[] = {"f2db7219baf30152975d4f81"};
//asic return 35 91 31 ae反序比较
const char g_nonce[] = {"359131ae"};
#else
const char g_midstate[] = {"4679ba4ec99876bf4bfe086082b400254df6c356451471139a3afa71e48f544a"};
const char g_data[] = {"87320b1a1426674f2fa722ce"};
//asic return 00 01 87 a2
const char g_nonce[] = "000187a2";
#endif
#else
const char g_full_data[] = { "0000000258007a06037bb0c899e253afc369f10c9e7762a8aa73d33b00000034000000009d5146878f7fda9f7f7f76f1c1aa6751f679e3aff3f722b2030b0eac"
"814f5d975201f3ba1972dbf2"
"ae319135"
"000000800000000000000000000000000000000000000000000000000000000000000000000000000000000080020000"
};
const char g_midstate[] = {"9a91ac02214239593aadae3e0e1ce8c6c8a7509542148383653981d2698b67c1"};//需要反序 (现在左侧为高位，右侧为低位 )
const char g_data[] = {"29a4001a4edce351072fb87f"};
const char g_nonce[] = {"92ec9b6e"};
#endif
#define test_DHASH 0
// Returns 1 if meets current buffer work, 0 if last buffer work
extern int hashtest(ASIC_TASK_P asic_task, uint32_t nonce)
{
BT_AS_INFO dev = &bitmain_asic_dev;
unsigned char hash1[32];
unsigned char hash2[32];
unsigned char i;
uint32_t *hash2_32 = (uint32_t *)hash1;
__attribute__ ((aligned (4))) sha2_context ctx;
memcpy(ctx.state, (void*)asic_task->midstate, 32);
#if test_DHASH
rev((unsigned char*)ctx.state, sizeof(ctx.state));
#endif
ctx.total[0] = 80;
ctx.total[1] = 00;
memcpy(hash1, (void*)asic_task->data, 12);
#if test_DHASH
rev(hash1, 12);
#endif
flip_swab(ctx.buffer, hash1, 12);
memcpy(hash1, &nonce, 4);
#if test_DHASH
rev(hash1, 4);
#endif
flip_swab(ctx.buffer + 12, hash1, 4);
sha2_finish( &ctx, hash1);
memset( &ctx, 0, sizeof( sha2_context ) );
sha2(hash1, 32, hash2);
flip32(hash1, hash2);
if (hash2_32[7] != 0) {
//printk_ratelimited("nonce error\n");
return 0;
}
else if( dev->nonce_diff !=0 )
{
for(i=0; i < dev->asic_configure.diff_sh_bit/32; i++)
{
if(be32toh(hash2_32[6 - i]) != 0)
break;
}
if(i == dev->asic_configure.diff_sh_bit/32)
if(be32toh(hash2_32[6 - dev->asic_configure.diff_sh_bit/32]) < ((uint32_t)0xffffffff >> (dev->asic_configure.diff_sh_bit%32)))
//if((hash2_32[6 - dev->asic_configure.diff_sh_bit/32] & ((0x01 << ((dev->asic_configure.diff_sh_bit)%32 + 1))-1)) == 0x00)
{
//printk_ratelimited(KERN_ERR "match diff %d hash2_32[%d]{0x%08x}\n", dev->asic_configure.diff_sh_bit,
//6 - dev->asic_configure.diff_sh_bit/32,be32toh(hash2_32[6 - dev->asic_configure.diff_sh_bit/32]));
//printk_ratelimited("diff cpare {0x%08x}\n", ((0x01 << ((dev->asic_configure.diff_sh_bit - 1)%32 + 1))-1));
gDiff_nonce_num++;
dev->diff1_num += (0x01UL << dev->nonce_diff);
dev->total_nonce_num++;
if(dev->net_diff_sh_bit != 0)
{
for(i=0; i < dev->net_diff_sh_bit/32; i++)
{
if(be32toh(hash2_32[6 - i]) != 0)
break;
}
if(i == dev->net_diff_sh_bit/32)
{
if(be32toh(hash2_32[6 - dev->net_diff_sh_bit/32]) < ((uint32_t)0xffffffff >> (dev->net_diff_sh_bit%32)))
{
printk_ratelimited(KERN_ERR "\n###Get Block##\n");
dev->get_blk_num++;
struct timex txc;
struct rtc_time tm;
struct file *fp_pwerr;
mm_segment_t old_fs;
char wr_buf[1024];
unsigned int wr_len = 0;
do_gettimeofday(&(txc.time));
rtc_time_to_tm(txc.time.tv_sec,&tm);
printk_ratelimited("UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec);
fp_pwerr = filp_open("/config/getblk", O_RDWR | O_CREAT | O_APPEND, 0644);
wr_len = sprintf(wr_buf, "UTC time:%d-%d-%d %d:%d:%d %08x%08x%08x%08x%08x%08x%08x%08x\n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec,
be32toh(hash2_32[7]),be32toh(hash2_32[6]),be32toh(hash2_32[5]),be32toh(hash2_32[4]),
be32toh(hash2_32[3]),be32toh(hash2_32[2]),be32toh(hash2_32[1]),be32toh(hash2_32[0]));
old_fs = get_fs();
set_fs(KERNEL_DS);
fp_pwerr->f_op->write(fp_pwerr, (char *)wr_buf, wr_len, &fp_pwerr->f_pos);
set_fs(old_fs);
filp_close(fp_pwerr, NULL);
}
}
}
return 2;
}
else if(be32toh(hash2_32[6 - dev->nonce_diff/32]) < ((uint32_t)0xffffffff >> (dev->nonce_diff%32)))
{
dev->diff1_num += (0x01UL << dev->nonce_diff);
dev->total_nonce_num++;
}
else
printk_ratelimited(KERN_ERR "match1 diff %d hash2_32{0x%08x}\n", dev->nonce_diff, be32toh(hash2_32[6 - dev->nonce_diff/32]));
return 1;
}
else
{
dev->diff1_num += (0x01UL << dev->asic_configure.diff_sh_bit);
dev->total_nonce_num++;
return 1;
}
if((dev->total_nonce_num & 0xffffffff) == 0xffffffff)
dev->cgminer_start_time = jiffies;
#if 0
else if( dev->asic_configure.diff_sh_bit !=0 )
{
if(htonl(hash2_32[6 - dev->asic_configure.diff_sh_bit/32]) < ((uint32_t)0xffffffff >> (dev->asic_configure.diff_sh_bit%32)))
//if((hash2_32[6 - dev->asic_configure.diff_sh_bit/32] & ((0x01 << ((dev->asic_configure.diff_sh_bit)%32 + 1))-1)) == 0x00)
{
printk_ratelimited(KERN_ERR "match diff %d hash2_32[%d]{0x%08x}\n", dev->asic_configure.diff_sh_bit,
6 - dev->asic_configure.diff_sh_bit/32,htonl(hash2_32[6 - dev->asic_configure.diff_sh_bit/32]));
//printk_ratelimited("diff cpare {0x%08x}\n", ((0x01 << ((dev->asic_configure.diff_sh_bit - 1)%32 + 1))-1));
gDiff_nonce_num++;
dev->total_nonce_num += 0x01 << dev->asic_configure.diff_sh_bit;
return 2;
}
else
return 1;
}
else
dev->total_nonce_num++;
return 1;
#endif
#if 0
unsigned char hash1[32];
unsigned char hash2[32];
uint32_t *hash2_32 = (uint32_t *)hash1;
//uint8_t i;
__attribute__ ((aligned (4))) sha2_context ctx;
//memcpy(ctx.state, asic_task->midstate, 32);
//rev((unsigned char*)ctx.state, sizeof(ctx.state));
memcpy(hash1, asic_task->midstate, 32);
//rev(hash1, 32);
//flip_swab(ctx.state, hash1, 32);//
flip32(ctx.state, hash1);
ctx.total[0] = 80;
ctx.total[1] = 0;
memcpy(hash1, (void*)asic_task->data, 12);
//rev(hash1, 12);
flip_swab(ctx.buffer, hash1, 12);
memcpy(hash1, &nonce, 4);
flip_swab(ctx.buffer + 12, hash1, 4);
printk_ratelimited("ctx:");
dump_hex(&ctx,sizeof(ctx));
sha2_finish( &ctx, hash1);
printk_ratelimited("hash1 in hashtest\n");
memset( &ctx, 0, sizeof( sha2_context ) );
sha2(hash1, 32, hash2);
flip32(hash1, hash2);
//printk_ratelimited("hash2_32[7]{%#x}hash2_32[0]{%#x}\n", hash2_32[7], hash2_32[0]);
if (be32toh(hash2_32[7]) != 0) {
printk_ratelimited("not work{%#x} nonce\n", le32_to_cpu(asic_task->work_id));
return 0;
}
return 1;
#endif
}
/* Returns 1 if meets current buffer work, 0 if last buffer work
extern int hashtest(ASIC_TASK_P asic_task, uint32_t nonce)
{
BT_AS_INFO dev = &bitmain_asic_dev;
gDiff_nonce_num++;
dev->diff1_num += (0x01UL << dev->nonce_diff);
dev->total_nonce_num++;
return 2;
if((dev->total_nonce_num & 0xffffffff) == 0xffffffff)
dev->cgminer_start_time = jiffies;
}
*/
static int bitmain_asic_open(struct inode *inode, struct file *file)
{
struct file *fp_hwver;
mm_segment_t old_fs;
char wr_buf[512];
unsigned int wr_len = 0;
BT_AS_INFO dev = &bitmain_asic_dev;
void *gpio3_virtual, *gpio1_virtual;
void *ctl_md_vaddr;
uint32_t value32;
uint32_t detect_ver = 0;
uint32_t save_ver = 0;
uint8_t i;
/* only allow one at a time */
if (test_and_set_bit(0, &bitmain_is_open))
return -EBUSY;
file->private_data = dev;
memset(dev, 0, sizeof(bitmain_asic_dev));
#if 1
ctl_md_vaddr = ioremap_nocache(CONTROL_MODULE_BASE, CONTROL_MODULE_Size);
//vesion ctl gpio3_19:bit 0 gpio3_21:bit1 gpio1_18 bit2
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9a4); //bit0
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x9ac); //bit1
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x848); //bit2
gpio3_virtual = ioremap_nocache(GPIO3_BASE, GPIO3_SIZE);
gpio1_virtual = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE);
value32 = ioread32(gpio3_virtual + GPIO_OE);
iowrite32(value32 | (((0x01<<19) | (0x01<<21))), gpio3_virtual + GPIO_OE); //set input
value32 = ioread32(gpio1_virtual + GPIO_OE);
iowrite32(value32 | (0x01<<18), gpio1_virtual + GPIO_OE); //set input
hardware_version = 0;
value32 = ioread32(gpio3_virtual+ GPIO_DATAIN );
detect_ver |= ((value32 >> 19)&0x01)<<0x00;
detect_ver |= ((value32 >> 21)&0x01)<<0x01;
value32 = ioread32(gpio1_virtual+ GPIO_DATAIN );
detect_ver |= ((value32 >> 18)&0x01)<<0x02;
printk_ratelimited("Detect hardware version = %d\n", detect_ver);
hardware_version = detect_ver;
#ifdef FIX_HARDWARE_VER
printk_ratelimited("fix hardware version\n");
#if defined C1_02 || defined S5
if((detect_ver == 0x03) || ((detect_ver == 0x04)))
hardware_version = 0x01;
else
hardware_version = FIX_HARDWARE_VER;
#elif defined S2
;
#else
hardware_version = FIX_HARDWARE_VER;
#endif
#endif
save_ver = hardware_version;
hardware_version = detect_ver;
printk_ratelimited("hardware_version = %#x\n", hardware_version);
fp_hwver = filp_open("/tmp/hwver", O_RDWR | O_CREAT | O_TRUNC, 0644);
wr_len = sprintf(wr_buf, "hardware_ver = 0x%02x\n", hardware_version);
old_fs = get_fs();
set_fs(KERNEL_DS);
fp_hwver->f_op->write(fp_hwver, (char *)wr_buf, wr_len, &fp_hwver->f_pos);
set_fs(old_fs);
filp_close(fp_hwver, NULL);
iounmap(gpio3_virtual);
iounmap(gpio1_virtual);
#if defined S2
printk_ratelimited("S2 ctrl board V1.0\n");
#endif
hardware_version = save_ver;
if(hardware_version == 0x01)
{
//Set GPIO1_13(Green) GPIO0_23(Red) to GPIO mode
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x834); //Green
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x824); //Red
#if defined C1_02 || defined S5
//Set GPIO1_13(Red) GPIO0_23(Green) to GPIO mode
if(detect_ver == 0x03)
{
GREEN = 0x01<<23;
RED = 0x01<<13;
printk_ratelimited("S5 ctrl board V1.0\n");
}
else if(detect_ver == 0x04)
{
GREEN = 0x01<<23;
RED = 0x01<<13;
printk_ratelimited("S5 ctrl board test V1.1\n");
iowrite32(PAD_PULLUP | PAD_REV | 0x7, ctl_md_vaddr + 0x828); //ip sig key gpio0_26
}
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x820); //hash test gpio0-22
#else
#if defined S4_PLUS
iowrite32(PAD_PULLUP | PAD_REV | 0x7, ctl_md_vaddr + 0x828); //ip sig key gpio0_26
#endif
GREEN = 0x01<<13;
RED = 0x01<<23;
#endif
}
else if(hardware_version == 0x02)
{
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x890); //Green
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x89C); //Red
GREEN = 0x01<<5;
RED = 0x01<<2;
}
else
{
//Set GPIO2_2(Green) GPIO2_5(Red) to GPIO mode
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x890); //Green
iowrite32(PAD_PULLUP | 0x7, ctl_md_vaddr + 0x89C); //Red
GREEN = 0x01<<2;
RED = 0x01<<5;
}
#if defined C1_02
if(hardware_version == 0x02) //GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x894); //recovery key
else
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x838); //recovery key
#else
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x838); //recovery key
#endif
iowrite32(PAD_REV | PAD_PULLUP | 0x7, ctl_md_vaddr + 0x950); //test key
//iounmap(ctl_md_vaddr);
#endif
if(hardware_version == 0x01)
{
#if defined C1_02 || defined S5
if((detect_ver == 0x03) || (detect_ver == 0x04))
{
dev->led_virtual1 = ioremap_nocache(GPIO0_BASE, GPIO0_SIZE); //green
value32 = ioread32(dev->led_virtual1 + GPIO_OE);
iowrite32(value32 & (~(GREEN)), dev->led_virtual1 + GPIO_OE); //set output
dev->led_virtual = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE); //red
value32 = ioread32(dev->led_virtual + GPIO_OE);
iowrite32(value32 & (~(RED)), dev->led_virtual + GPIO_OE); //set output
}
else
#endif
{
dev->led_virtual1 = ioremap_nocache(GPIO1_BASE, GPIO1_SIZE);
value32 = ioread32(dev->led_virtual1 + GPIO_OE);
iowrite32(value32 & (~(GREEN)), dev->led_virtual1 + GPIO_OE); //set output
dev->led_virtual = ioremap_nocache(GPIO0_BASE, GPIO0_SIZE);
value32 = ioread32(dev->led_virtual + GPIO_OE);
iowrite32(value32 & (~(RED)), dev->led_virtual + GPIO_OE); //set output
}
}
else
{
dev->led_virtual = ioremap_nocache(GPIO2_BASE, GPIO2_SIZE);
value32 = ioread32(dev->led_virtual + GPIO_OE);
iowrite32(value32 & (~(GREEN)), dev->led_virtual + GPIO_OE); //set output
value32 = ioread32(dev->led_virtual + GPIO_OE);
iowrite32(value32 & (~(RED)), dev->led_virtual + GPIO_OE); //set output
}
dev->task_buffer_size = TASK_BUFFER_NUMBER + TASK_PRE_LEFT;
dev->task_buffer = (ASIC_TASK_P)kmalloc(sizeof(*dev->task_buffer)*dev->task_buffer_size, GFP_KERNEL);
//dev->task_buffer_wr = 10;
dev->asic_status_data.data_type = BM_STATUS_DATA;
dev->asic_status_data.version= 0x00;
dev->asic_status_data.chain_num = CHAIN_SIZE;
dev->asic_configure.diff_sh_bit = 0;
dev->send_to_fpga_interval = 500;
for(i = 0; i < dev->asic_status_data.chain_num; i++)
dev->asic_status_data.chain_asic_num[i] = 32;
spin_lock_init(&dev->lock);
mutex_init(&dev->result_lock);
mutex_init(&dev->to_work_lock);
dev->asic_configure.timeout_data = 7;
ChangePWM(dev, 0);
//bitmain_set_voltage(dev, 0x0750);
dev->last_nonce_timeout = 0; //挖矿时会响一下
//detect_chain_num(dev);
dev->send_to_fpga_work_wq = create_singlethread_workqueue(DRV_NAME);
INIT_WORK(&dev->send_to_fpga_work, send_to_pfga_work);
#if PRNT_TIMER_EN
init_timer(&prnt_timer);
prnt_timer.function = Prnt;
prnt_timer.expires = jiffies + 500*HZ/1000;
//add_timer(&prnt_timer);
#endif
init_beep(dev);
value32 = ioread32(gpio0_vaddr + GPIO_OE);
//iowrite32(0x01<<22, gpio0_vaddr + GPIO_SETDATAOUT);
iowrite32(value32 & (~(0x01<<22)), gpio0_vaddr + GPIO_OE); //set output
if(detect_ver == 0x04)
{
value32 = ioread32(gpio0_vaddr + GPIO_OE);
//iowrite32(0x01<<22, gpio0_vaddr + GPIO_SETDATAOUT);
iowrite32(value32 | (0x01<<26), gpio0_vaddr + GPIO_OE); //set input
}
printk_ratelimited(KERN_ERR "bitmain_asic_open ok\n");
return 0;
}
static int bitmain_asic_close(struct inode *inode, struct file *file)
{
BT_AS_INFO dev = &bitmain_asic_dev;
//uint32_t i;
//struct ASIC_TASK asic_task;
wait_queue_head_t timeout_wq;
init_waitqueue_head(&timeout_wq);
#if PRNT_TIMER_EN
del_timer(&prnt_timer);
#endif
destroy_workqueue(dev->send_to_fpga_work_wq);
if(1)
{
#if 0
for(i = 0; i < dev->asic_status_data.chain_num; i++)
{
memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate));
memset(asic_task.data, 0x00, sizeof(asic_task.data));
if(i == 0)
send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task);
else
send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task);
}
#endif
stop_work_to_all_chain(dev);
}
//send_work_to_fpga(true, 0, dev, &asic_task);
iowrite32(0x01<<8, gpio2_vaddr + GPIO_SETDATAOUT);
sleep_on_timeout(&timeout_wq, 100 * HZ/1000);//100ms
dev->asic_configure.timeout_data = 7;
dev->timeout_valid = true;
ChangePWM(dev, 0);
nonce_query(dev);
dev->timeout_valid = false;
if( dev->asic_configure.bauddiv != 26)
{
//iowrite32(0x01<<6, gpio2_vaddr + GPIO_SETDATAOUT);
set_baud(dev, 26);
//iowrite32(0x01<<6, gpio2_vaddr + GPIO_CLEARDATAOUT);
bitmain_set_voltage(dev,0x0725);
}
iowrite32(0x01<<8, gpio2_vaddr + GPIO_CLEARDATAOUT);
//test
iowrite32(0x01<<22, gpio0_vaddr + GPIO_CLEARDATAOUT);
//close beep
iowrite32(0x01<<20, gpio0_vaddr + GPIO_CLEARDATAOUT);
iounmap(dev->beep_virtual_addr);
clear_bit(0, &bitmain_is_open);
//bitmain_asic_open_usb(dev);
kfree((void*)(dev->task_buffer));
//free_irq(TIMER_INTERRUPT, NULL);
//spi_close();
printk_ratelimited(KERN_ERR "bitmain_asic_close\n");
return 0;
}
void stop_work_to_all_chain(BT_AS_INFO dev)
{
uint32_t i;
struct ASIC_TASK asic_task;
printk_ratelimited(KERN_ERR "stop send work to all chain\n");
memset(&asic_task, 0x00, sizeof(asic_task));
for(i = 0; i < dev->asic_status_data.chain_num; i++)
{
memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate));
memset(asic_task.data, 0x00, sizeof(asic_task.data));
if(i == 0)
send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task);
else
send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task);
}
}
void check_chain_power(BT_AS_INFO dev)
{
uint32_t bgNonce_average;
uint32_t time_elasp_ms = 0;
uint32_t i;
uint8_t chain_nu;
//struct ASIC_TASK asic_task;
static unsigned long simulate_power_err_time = 0;
wait_queue_head_t timeout_wq;
unsigned char cmd_buf[4] = {0};
if((dev->cgminer_start == true))
{
if(simulate_power_err_time == 0)
{
simulate_power_err_time = jiffies + 5 * 60 * 1000 * HZ/1000;
}
time_elasp_ms = jiffies_to_msecs(jiffies - dev->cgminer_start_time);
//printk_ratelimited("time_elasp_jiffies{%ld}\n", jiffies - dev->cgminer_start_time);
//printk_ratelimited("jiffies{%ld}dev->cgminer_start_time{%ld}", jiffies, dev->cgminer_start_time);
//printk_ratelimited("time_elasp_ms =%ldms dev->total_nonce_num{%ld}\n", time_elasp_ms, dev->total_nonce_num);
//bgNonce_average = ((uint32_t)dev->total_nonce_num / (time_elasp_ms / 1000)) * (CHAIN_POWER_TIME_INTERAL*60);//平均5分钟
if(dev->asic_status_data.chain_num !=0 )
bgNonce_average = (uint32_t)dev->total_nonce_num/dev->asic_status_data.chain_num;
else
bgNonce_average = (uint32_t)dev->total_nonce_num;
if((time_elasp_ms / (1000 * CHAIN_POWER_TIME_INTERAL*60)) == 0)
{
if(bgNonce_average < 8)
bgNonce_average = 1;
else
bgNonce_average /= 8;
}
else
{
bgNonce_average = bgNonce_average / (time_elasp_ms / (1000 * CHAIN_POWER_TIME_INTERAL*60));//平均5分钟
bgNonce_average /= 8;
}
for (i = 0; i < dev->asic_status_data.chain_num; i++)
{
chain_nu = dev->chain_map[i];
//printk_ratelimited("bgNonce_average{%d}\n", bgNonce_average);
//printk_ratelimited("chain%d Chain_nonce_nu[%ld] Chain_nonce_nu_last[%ld]\n", chain_nu,Chain_nonce_nu[chain_nu],Chain_nonce_nu_last[chain_nu]);
if(Chain_nonce_nu[chain_nu] >= Chain_nonce_nu_last[chain_nu])
{
if(((Chain_nonce_nu[chain_nu] - Chain_nonce_nu_last[chain_nu]) < bgNonce_average) || (bgNonce_average == 0))
//if(time_after(jiffies, simulate_power_err_time))
{
struct timex txc;
struct rtc_time tm;
struct file *fp_pwerr;
mm_segment_t old_fs;
char wr_buf[512];
unsigned int wr_len = 0;
do_gettimeofday(&(txc.time));
rtc_time_to_tm(txc.time.tv_sec,&tm);
//printk_ratelimited("UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec);
fp_pwerr = filp_open("/config/power_rst", O_RDWR | O_CREAT | O_APPEND, 0644);
wr_len = sprintf(wr_buf, "UTC time :%d-%d-%d %d:%d:%d \n",tm.tm_year+1900,tm.tm_mon + 1, tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec);
old_fs = get_fs();
set_fs(KERNEL_DS);
fp_pwerr->f_op->write(fp_pwerr, (char *)wr_buf, wr_len, &fp_pwerr->f_pos);
set_fs(old_fs);
filp_close(fp_pwerr, NULL);
dev->restarting_hash = true;
mod_timer(&prnt_timer, jiffies + 5 * 1000 * HZ/1000);
i = 0;
while(timer_pending(&prnt_timer))
{
del_timer(&prnt_timer);
if(i++ > 200)
break;
}
if(bgNonce_average == 0)
printk_ratelimited("!!!!!!!!!!----no hash power OK\n\n");
printk_ratelimited("remap chain%d(hardware chain%d) power err\n", i, chain_nu);
printk_ratelimited("bgNonce_average{%d}chain_nonce_nu{%d}last{%d}\n", bgNonce_average, Chain_nonce_nu[chain_nu], Chain_nonce_nu_last[chain_nu]);
#if 0
for(i = 0; i < dev->asic_status_data.chain_num; i++)
{
memset(asic_task.midstate, 0x00, sizeof(asic_task.midstate));
memset(asic_task.data, 0x00, sizeof(asic_task.data));
if(i == 0)
send_work_to_fpga(true, 0x80|dev->chain_map[i], dev, &asic_task);
else
send_work_to_fpga(false, 0x80|dev->chain_map[i], dev, &asic_task);
}
#endif
stop_work_to_all_chain(dev);
set_baud(dev, 26);
printk_ratelimited(KERN_ERR "Detect device for anyone power err\n");
cmd_buf[0] = 9;
cmd_buf[1] = 0x10; //16-23
cmd_buf[2] = 0x1f; //8-13
cmd_buf[0] |= 0x80;
//cmd_buf[3] = CRC5(cmd_buf, 4*8 - 5);
cmd_buf[3] = 0x00; //故意错误crc 只是修改fpga 波特率
send_BC_to_fpga(i, cmd_buf);
rst_hash_asic(dev);
//send_work_to_fpga(true, dev, &asic_task);
clear_fpga_nonce_buffer(dev);
init_waitqueue_head(&timeout_wq);
interruptible_sleep_on_timeout(&timeout_wq, 1000 * HZ/1000);//300ms
#if 1
rst_hash_asic(dev);
//send_work_to_fpga(true, dev, &asic_task);
clear_fpga_nonce_buffer(dev);
init_waitqueue_head(&timeout_wq);
interruptible_sleep_on_timeout(&timeout_wq, 1100 * HZ/1000);//300ms
#endif
//detect_chain_num(dev);
set_frequency(dev, dev->asic_configure.freq_vlaue);
asic_result_status_rd = asic_result_status_wr = asic_result_status_full = 0;
asic_result_rd = asic_result_wr = asic_result_full = 0;
//gDiff_nonce_num = gNonce_num = gNonce_Err = gNonce_miss = 0;
//gSubmit_nonce_num = 0;
dev->restarting_hash = false;
prnt_timer.expires = jiffies + dev->send_to_fpga_interval* HZ/1000;
add_timer(&prnt_timer);
mod_timer(&prnt_timer, jiffies + dev->send_to_fpga_interval* HZ/1000);
simulate_power_err_time = 0;
break;
}
}
Chain_nonce_nu_last[chain_nu] = Chain_nonce_nu[chain_nu];
}
}
}
#define MAX_ASIC_NUM 64
void check_asic_status(BT_AS_INFO dev)
{
uint32_t bgNonce_average;
uint32_t i, j;
static uint32_t last_asic_nonce[CHAIN_SIZE][MAX_ASIC_NUM] = {0};
static uint32_t last_gNonce_num = 0;
if ((dev->cgminer_start == true) && (gTotal_asic_num !=0))
{
//printk_ratelimited(KERN_ERR "check_asic_status\n");
if (gNonce_num > gTotal_asic_num * 8)
{
if (gNonce_num > 0x7fffffff)
{
for (i = 0; i < CHAIN_SIZE; i++)
{
for (j = 0; j < gChain_Asic_num[i]; j++)
{
gAsic_cnt[i][j] >>= 2;
last_asic_nonce[i][j] >>=2;
}
}
gNonce_num >>= 2;
last_gNonce_num >>=2;
}
bgNonce_average = (gNonce_num - last_gNonce_num )/ gTotal_asic_num / 8;
last_gNonce_num = gNonce_num;
for (i = 0; i < CHAIN_SIZE; i++)
{
for (j = 0; j < gChain_Asic_num[i]; j++)
{
if ((gAsic_cnt[i][j] - last_asic_nonce[i][j]) < bgNonce_average)
{
gChain_Asic_status[i][j/32] &= ~(0x01 << (j%32));
//printk_ratelimited("gNonce_num{%d}gAsic_cnt[%d][%d]{%d}\n", gNonce_num, i, j, gAsic_cnt[i][j]);
}
else
{
gChain_Asic_status[i][j/32] |= (0x01 << (j%32));
if((dev->chain_asic_exist[i][j/32] & (0x01 << (j%32))) == 0)
dev->chain_asic_exist[i][j/32] |= (0x01 << (j%32));
}
if((gAsic_cnt[i][j] !=0) && ((dev->chain_asic_exist[i][j/32] & (0x01 << (j%32))) == 0))
{
dev->chain_asic_exist[i][j/32] |= (0x01 << (j%32));
}
last_asic_nonce[i][j] = gAsic_cnt[i][j];
}
}
}
}
}
#define LOW_PWM_PERCENT 20 //10、40
#define TEMP_INTERVAL 2 //温度变化多少 调整 PWM
//60度对应100，35度对应0吧, 实际为3；
#define PWM_ADJUST_FACTOR ((100 - LOW_PWM_PERCENT)/(60-35))
//#define PWM_SCALE 1250 //25M=40ns 20KHz 周期
#define PWM_SCALE 50 //1M=1us 20KHz 周期
//#define PWM_ADJ_SCALE (12/10) // 1 normal
#define PWM_ADJ_SCALE 9/10 // 1 normal
void ChangePWM(BT_AS_INFO dev, unsigned int pwm_percent)
{
if (fan_custom)
{