Wrap Makefile include statements in ifneq ($(MAKECMDGOALS),clean) to

prevent rebulding dependency rules when doing make clean

Author: highperformancecoder

examples/Makefile

@@ -90,7 +90,9 @@ endif
 depend: $(OBJS:.o=.d) $(EXES:=.d)
 	cat *.d >depend
 
+ifneq ($(MAKECMDGOALS),clean)
 include depend
+endif
 
 .cc.o:
 	$(CPLUSPLUS) $(CFLAGS) -c -o $@ $<

java/Makefile

@@ -57,7 +57,9 @@ endif
 depend: $(OBJS:.o=.d) $(EXES:=.d) $(DLLS:lib%.so=%.d)
 	cat *.d >depend
 
+ifneq ($(MAKECMDGOALS),clean)
 include depend
+endif
 
 .cc.o:
 	$(CPLUSPLUS) $(CFLAGS) -c -o $@ $<

javaExamples/Makefile

@@ -66,7 +66,9 @@ endif
 depend: $(OBJS:.o=.d) $(EXES:=.d) $(DLLS:lib%.so=%.d)
 	cat *.d >depend
 
+ifneq ($(MAKECMDGOALS),clean)
 include depend
+endif
 
 .cc.o:
 	$(CPLUSPLUS) $(CFLAGS) -c -o $@ $<

mpi-examples/Makefile

@@ -88,7 +88,9 @@ endif
 depend: $(OBJS:.o=.d) $(EXES:=.d)
 	cat *.d >depend
 
+ifneq ($(MAKECMDGOALS),clean)
 include depend
+endif
 
 .cc.o:
 	$(CPLUSPLUS) $(CFLAGS) -c $<

pythonExample/Makefile

@@ -15,7 +15,9 @@ example.so: $(OBJS)
 .cc.d: 
 	gcc $(CFLAGS) -w -MM -MG $< >$@
 
+ifneq ($(MAKECMDGOALS),clean)
 include $(OBJS:.o=.d) $(EXES:=.d)
+endif
 
 clean: 
 	rm -f *.o  *~ "\#*\#" core *.exh *.exc *.d *.cd *,D 

test/Makefile

@@ -100,7 +100,9 @@ endif
 depend: $(OBJS:.o=.d) $(EXES:=.d)
 	cat *.d >depend
 
+ifneq ($(MAKECMDGOALS),clean)
 include depend
+endif
 
 .cc.o:
 	$(CPLUSPLUS) $(CFLAGS) -c -o $@ $<

test/c++11/Makefile

@@ -91,7 +91,9 @@ endif
 depend: $(OBJS:.o=.d) $(EXES:=.d)
 	cat *.d >depend
 
+ifneq ($(MAKECMDGOALS),clean)
 include depend
+endif
 
 .cc.o:
 	$(CPLUSPLUS) $(CFLAGS) -c -o $@ $<