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port_map_tmr.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX220/RX230/RX231 グループ・ポート・マッピング (TMR)
@author 平松邦仁 ([email protected])
@copyright Copyright (C) 2024, 2025 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#if defined(SIG_RX220)
#include "RX220/peripheral.hpp"
#include "RX220/port.hpp"
#include "RX220/mpc.hpp"
#elif defined(SIG_RX230) || defined(SIG_RX231)
#include "RX231/peripheral.hpp"
#include "RX231/port.hpp"
#include "RX231/mpc.hpp"
#endif
#include "RX600/port_map_order.hpp"
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief RX220/RX231 TMR ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map_tmr : public port_map_order {
static bool tmr0_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0'0101 : 0; // ok
switch(ch) {
case CHANNEL::TMO: // TMO0
// P22
// PB3
// PH1
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel;
PORT2::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel;
PORTB::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTH::PMR.B1 = 0;
MPC::PH1PFS.PSEL = sel;
PORTH::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMCI: // TMCI0
// P21
// PB1
// PH3
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B1 = 0;
MPC::P21PFS.PSEL = sel;
PORT2::PMR.B1 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B1 = 0;
MPC::PB1PFS.PSEL = sel;
PORTB::PMR.B1 = ena;
break;
case ORDER::THIRD:
PORTH::PMR.B3 = 0;
MPC::PH3PFS.PSEL = sel;
PORTH::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMRI: // TMRI0
// P20
// PA4
// PH2
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B0 = 0;
MPC::P20PFS.PSEL = sel;
PORT2::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B4 = 0;
MPC::PA4PFS.PSEL = sel;
PORTA::PMR.B4 = ena;
break;
case ORDER::THIRD:
PORTH::PMR.B2 = 0;
MPC::PH2PFS.PSEL = sel;
PORTH::PMR.B2 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tmr1_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0'0101 : 0; // ok
switch(ch) {
case CHANNEL::TMO: // TMO1
// P17
// P26
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel;
PORT1::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORT2::PMR.B6 = 0;
MPC::P26PFS.PSEL = sel;
PORT2::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMCI: // TMCI1
// P12
// P54
// PC4
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B2 = 0;
MPC::P12PFS.PSEL = sel;
PORT1::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORT5::PMR.B4 = 0;
MPC::P54PFS.PSEL = sel;
PORT5::PMR.B4 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel;
PORTC::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMRI: // TMRI1
// P24
// PB5
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel;
PORT2::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel;
PORTB::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tmr2_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0'0101 : 0; // ok
switch(ch) {
case CHANNEL::TMO: // TMO2
// P16
// PC7
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = sel;
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTC::PMR.B7 = 0;
MPC::PC7PFS.PSEL = sel;
PORTC::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMCI: // TMCI2
// P15
// P31
// PC6
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel;
PORT1::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORT3::PMR.B1 = 0;
MPC::P31PFS.PSEL = sel;
PORT3::PMR.B1 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B6 = 0;
MPC::PC6PFS.PSEL = sel;
PORTC::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMRI: // TMRI2
// P14
// PC5
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = sel;
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel;
PORTC::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tmr3_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0'0101 : 0; // ok
switch(ch) {
case CHANNEL::TMO: // TMO3
// P13
// P32
// P55
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B3 = 0;
MPC::P13PFS.PSEL = sel;
PORT1::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORT3::PMR.B2 = 0;
MPC::P32PFS.PSEL = sel;
PORT3::PMR.B2 = ena;
break;
case ORDER::THIRD:
PORT5::PMR.B5 = 0;
MPC::P55PFS.PSEL = sel;
PORT5::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMCI: // TMCI3
// P27
// P34
// PA6
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B7 = 0;
MPC::P27PFS.PSEL = sel;
PORT2::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORT3::PMR.B4 = 0;
MPC::P34PFS.PSEL = sel;
PORT3::PMR.B4 = ena;
break;
case ORDER::THIRD:
PORTA::PMR.B6 = 0;
MPC::PA6PFS.PSEL = sel;
PORTA::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::TMRI: // TMRI3
// P30
// P33
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B0 = 0;
MPC::P30PFS.PSEL = sel;
PORT3::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORT3::PMR.B3 = 0;
MPC::P33PFS.PSEL = sel;
PORT3::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
public:
//-----------------------------------------------------------------//
/*!
@brief TMR 関係、チャネル別ポート切り替え
@param[in] per 周辺機器タイプ
@param[in] ch チャネル
@param[in] ena 無効にする場合「false」
@param[in] odr 候補選択
@return 無効な周辺機器の場合「false」
*/
//-----------------------------------------------------------------//
static bool turn(peripheral per, CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST) noexcept
{
if(odr == ORDER::BYPASS) return true;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(per) {
case peripheral::TMR0:
ret = tmr0_(ch, ena, odr);
break;
case peripheral::TMR1:
ret = tmr1_(ch, ena, odr);
break;
case peripheral::TMR2:
ret = tmr2_(ch, ena, odr);
break;
case peripheral::TMR3:
ret = tmr3_(ch, ena, odr);
break;
default:
ret = false;
break;
}
MPC::PWPR = device::MPC::PWPR.B0WI.b();
return ret;
}
};
}