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port_map_tpu.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX65N/RX651 グループ・ポート・マッピング (TPU) @n
・TPU 型に従って、タイマー用ポートを設定 @n
TPU0, TPU1, TPU2, TPU3, TPU4, TPU5
@author 平松邦仁 ([email protected])
@copyright Copyright (C) 2022, 2024 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#include "RX65x/peripheral.hpp"
#include "RX64M/port.hpp"
#include "RX65x/mpc.hpp"
#include "RX600/port_map_order.hpp"
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief TPU ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map_tpu : public port_map_order {
static bool tpu0_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
// TIOCA0:
switch(odr) {
// P86
// PA0
case ORDER::FIRST:
PORT8::PMR.B6 = 0;
MPC::P86PFS.PSEL = sel;
PORT8::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B0 = 0;
MPC::PA0PFS.PSEL = sel;
PORTA::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
// TIOCB0:
switch(odr) {
// P17
// PA1
case ORDER::FIRST:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel;
PORT1::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel;
PORTA::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C:
// TIOCC0:
switch(odr) {
// P32
// P85
case ORDER::FIRST:
PORT3::PMR.B2 = 0;
MPC::P32PFS.PSEL = sel;
PORT3::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORT8::PMR.B5 = 0;
MPC::P85PFS.PSEL = sel;
PORT8::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D:
// TIOCD0:
switch(odr) {
// P33
// PA3
case ORDER::FIRST:
PORT3::PMR.B3 = 0;
MPC::P33PFS.PSEL = sel;
PORT3::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B3 = 0;
MPC::PA3PFS.PSEL = sel;
PORTA::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu1_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
// TIOCA1:
switch(odr) {
// P56
// PA4
case ORDER::FIRST:
PORT5::PMR.B6 = 0;
MPC::P56PFS.PSEL = sel;
PORT5::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B4 = 0;
MPC::PA4PFS.PSEL = sel;
PORTA::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
// TIOCB1:
switch(odr) {
// P16
// PA5
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = sel;
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B5 = 0;
MPC::PA5PFS.PSEL = sel;
PORTA::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu2_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
// TIOCA2:
switch(odr) {
// P87
// PA6
case ORDER::FIRST:
PORT8::PMR.B7 = 0;
MPC::P87PFS.PSEL = sel;
PORT8::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B6 = 0;
MPC::PA6PFS.PSEL = sel;
PORTA::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
// TIOCB2:
switch(odr) {
// P15
// PA7
case ORDER::FIRST:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel;
PORT1::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B7 = 0;
MPC::PA7PFS.PSEL = sel;
PORTA::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu3_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
// TIOCA3:
switch(odr) {
// P21
// PB0
case ORDER::FIRST:
PORT2::PMR.B1 = 0;
MPC::P21PFS.PSEL = sel;
PORT2::PMR.B1 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B0 = 0;
MPC::PB0PFS.PSEL = sel;
PORTB::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
// TIOCB3:
switch(odr) {
// P20
// PB1
case ORDER::FIRST:
PORT2::PMR.B0 = 0;
MPC::P20PFS.PSEL = sel;
PORT2::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B1 = 0;
MPC::PB1PFS.PSEL = sel;
PORTB::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C:
// TIOCC3:
switch(odr) {
// P22
// PB2
case ORDER::FIRST:
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel;
PORT2::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B2 = 0;
MPC::PB2PFS.PSEL = sel;
PORTB::PMR.B2 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D:
// TIOCD3:
switch(odr) {
// P23
// PB3
case ORDER::FIRST:
PORT2::PMR.B3 = 0;
MPC::P23PFS.PSEL = sel;
PORT2::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel;
PORTB::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu4_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
// TIOCA4:
switch(odr) {
// P25
// PB4
case ORDER::FIRST:
PORT2::PMR.B5 = 0;
MPC::P25PFS.PSEL = sel;
PORT2::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B4 = 0;
MPC::PB4PFS.PSEL = sel;
PORTB::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
// TIOCB4:
switch(odr) {
// P24
// PB5
case ORDER::FIRST:
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel;
PORT2::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel;
PORTB::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu5_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
// TIOCA5:
switch(odr) {
// P13
// PB6
case ORDER::FIRST:
PORT1::PMR.B3 = 0;
MPC::P13PFS.PSEL = sel;
PORT1::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B6 = 0;
MPC::PB6PFS.PSEL = sel;
PORTB::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
// TIOCB5:
switch(odr) {
// P14
// PB7
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = sel;
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B7 = 0;
MPC::PB7PFS.PSEL = sel;
PORTB::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
public:
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief タイマー系、チャネル別ポート切り替え
@param[in] per 周辺機器タイプ
@param[in] ch チャネル
@param[in] ena 無効にする場合場合「false」
@param[in] odr 候補を選択する場合
@return 無効な周辺機器の場合「false」
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
static bool turn(peripheral per, CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST) noexcept
{
if(odr == ORDER::BYPASS) return true;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(per) {
case peripheral::TPU0:
ret = tpu0_(ch, ena, odr);
break;
case peripheral::TPU1:
ret = tpu1_(ch, ena, odr);
break;
case peripheral::TPU2:
ret = tpu2_(ch, ena, odr);
break;
case peripheral::TPU3:
ret = tpu3_(ch, ena, odr);
break;
case peripheral::TPU4:
ret = tpu4_(ch, ena, odr);
break;
case peripheral::TPU5:
ret = tpu5_(ch, ena, odr);
break;
default:
ret = false;
break;
}
MPC::PWPR = MPC::PWPR.B0WI.b();
return ret;
}
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief TPU クロック入力切り替え
@param[in] clk クロック型
@param[in] ena 無効にする場合場合「false」
@param[in] odr 候補を選択する場合
@return 無効な周辺機器の場合「false」
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
static bool turn_clock(CHANNEL clk, bool ena = true, ORDER odr = ORDER::FIRST) noexcept
{
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(clk) {
case CHANNEL::CLK_A:
// TCLKA:
switch(odr) {
// P14
// PC2
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = ena ? 0b000100 : 0;
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTC::PMR.B2 = 0;
MPC::PC2PFS.PSEL = ena ? 0b000011 : 0;
PORTC::PMR.B2 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::CLK_B:
// TCLKB:
switch(odr) {
// P15
// PA3
// PC3
case ORDER::FIRST:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = ena ? 0b000100 : 0;
PORT1::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B3 = 0;
MPC::PA3PFS.PSEL = ena ? 0b000100 : 0;
PORTA::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B3 = 0;
MPC::PC3PFS.PSEL = ena ? 0b000011 : 0;
PORTC::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::CLK_C:
// TCLKC:
switch(odr) {
// P16
// PB2
// PC0
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = ena ? 0b000100 : 0;
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B2 = 0;
MPC::PB2PFS.PSEL = ena ? 0b000100 : 0;
PORTB::PMR.B2 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B0 = 0;
MPC::PC0PFS.PSEL = ena ? 0b000011 : 0;
PORTC::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::CLK_D:
// TCLKD:
switch(odr) {
// P17
// PB3
// PC1
case ORDER::FIRST:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = ena ? 0b000100 : 0;
PORT1::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = ena ? 0b000100 : 0;
PORTB::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B1 = 0;
MPC::PC1PFS.PSEL = ena ? 0b000011 : 0;
PORTC::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
MPC::PWPR = MPC::PWPR.B0WI.b();
return ret;
}
};
}